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IDT49C465AG Datasheet(PDF) 34 Page - Integrated Device Technology

Part # IDT49C465AG
Description  32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT49C465AG Datasheet(HTML) 34 Page - Integrated Device Technology

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11.7
34
IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TIMING DIAGRAMS — 64-BIT CONFIGURATION
NOTE:
2552 drw 25
1. Assumes that Memory Data and Checkbits are valid at least 4ns (Com.) before MLE goes HIGH.
Figure 13. 64-Bit Correct Timing (Upper Slice)
t CMLH
MLE
MD 0–31
MOE
min.
Parameter
Name
Propagation Delay
From
To
Min./
Max.
(OUTPUT)
CBI
Valid Checkbits In
t CMLS
t MMLH
t MMLS
t MEMxZ
t MLS
t CMLH
t CMLS
t MMLH
t MMLS
t MEMxZ
CBI Hold to MLE = Low
CBI Set-up to MLE = Low
MDIN Hold to MLE = Low
MDIN Set-up to MLE = Low
MOE = High to MDOUT
Disabled
min.
min.
min.
max.
t PLS
t BESZx
t SESZx
t CS
t MSY
t MLP
t PLP
t BEPZx
t SEP
Corrected DATAOUT
Parity Out
t MLS
t PLS
t BESZx
t SESZx
t CS
t MSY
t MLP
t PLP
t BEPZx
t SEP
MLEIN = High to SDOUT
PLE = Low to SDOUT
BEN = High to SDOUT Enabled
SOE = Low to SDOUT Enabled
CBI to Corrected SDOUT
MDIN to Corrected SDOUT
MLE = High to Parity Out
PLE = Low to Parity Out
BEN = High to Parity Out
SOE = Low to Parity Out
max.
max.
max.
max.
max.
max.
max.
max.
max.
max.
PLE
BEN
SOE
SD0–31
P0–3
t MP
t MP
MDIN to Parity Out
max.
Partial Checkbits/ Syndrome Out
SYO
t MS
t MS
MDIN to Corrected SDOUT
max.
64-BIT
U/L Slice
to
1
2
3
4
5
to
1
2
3
4
5
(1)
(1)
(1)
(1)
(1)
(1)
Valid DATAIN


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