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5429FCT520ATP Datasheet(PDF) 2 Page - Integrated Device Technology |
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5429FCT520ATP Datasheet(HTML) 2 Page - Integrated Device Technology |
2 / 7 page 6.2 2 IDT29FCT520AT/BT/CT/DT, 521AT/BT/CT/DT MULTILEVEL PIPELINE REGISTERS MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN CONFIGURATIONS NOTE: 1. I = 3 for hold. Figure 1. Data Loading in 2-Level Operation DUAL 2-LEVEL SINGLE 4-LEVEL 2619 drw 04 A1 A2 B1 B2 A1 A2 B1 B2 I = 2 I = 1 A1 A2 B1 B2 A1 A2 B1 B2 I = 2 I = 1 A1 A2 B1 B2 I = 0 A1 A2 B1 B2 I = 0 IDT29FCT520T IDT29FCT521T 5 6 7 8 9 10 11 12 GND 1 2 3 4 24 23 22 21 20 19 18 17 Vcc 16 15 14 13 P24-1 D24-1 SO24-2 SO24-7 SO24-8* & E24-1 S 0 S 1 Y 0 Y 1 Y 2 Y 3 Y 4 Y 5 OE I 0 I 1 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 CLK Y 6 Y 7 *FCT520 only DEFINITION OF FUNCTIONAL TERMS Pin Names Description Dn Register input Port. CLK Clock input. Enter data into registers on LOW- to-HIGH transitions. I0, I1 Instruction inputs. See Figure 1 and in- struction Control Tables. S0, S1 Multiplexer select. Inputs either register A1, A2, B1 or B2 data to be available at the output port. OE Output enable for 3-state output port. Yn Register output port. 2619 tbl 01 REGISTER SELECTION S1 S0 Register 00 B2 01 B1 10 A2 11 A1 2619 tbl 02 2619 drw 03 5 6 7 8 9 10 11 L28-1 25 24 23 22 21 20 19 INDEX D1 D2 D3 D4 D5 D6 NC NC Y0 Y1 Y2 Y3 Y4 Y5 12 13 14 15 16 17 18 43 2 1 28 27 26 2619 drw 02 DIP/SOIC/SSOP/QSOP/CERPACK TOP VIEW LCC TOP VIEW |
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