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IDT49C466 Datasheet(PDF) 4 Page - Integrated Device Technology

Part No. IDT49C466
Description  64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT49C466 Datasheet(HTML) 4 Page - Integrated Device Technology

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11.7
4
IDT49C466/A Flow-thruEDC
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Pin Name
I/O
Description
Data Buses
SD0-63
I/O
System Data Bus: is a bidirectional 64-bit bus interfacing to the system or CPU. When System Output
Enable,
SOE, is HIGH or Byte Enable, BE0-7, is LOW, data can be input. When System Output Enable,
SOE, is LOW and Byte Enable, BE0-7, is HIGH, the SD bus output drivers are enabled.
MD0-63
I/O
Memory Data Bus: is a bidirectional 64-bit bus interfacing to the memory. During a read cycle, (
MOE
HIGH) memory data is input for error detection and correction. Data is output on the Memory Data
Bus, when
MOE is LOW.
CBI0-7
I
Check Bit Inputs: interface to the check bit memory.
CBSYN0-7
O
Check Bit/Syndrome Output: When
MOE is LOW the generated check bits are output. When
CBSEL is HIGH and
MOE is HIGH, the syndrome bits are output. The bus is tristated when MOE =
1 and CBSEL = 0.
P0-7
I/O
Parity for bytes 0 to 7: These pins are parity inputs when the corresponding Byte Enable (BE) is LOW
or
SOE is HIGH, and are used to generate the parity error signal (PERR). These pins are outputs when
the corresponding Byte Enable (BE) is HIGH and
SOE is LOW.
Control Inputs
SOE
I
System Output Enable: enables system data bus output drivers if the corresponding Byte Enable
(BE0-7) is HIGH.
BE0-7
I
Byte Enable: is used along with
SOE, to enable the System Data outputs for a particular byte. For
example, if BE1 is HIGH, the System data outputs for byte 1 (SD8-15) are enabled. The BE0-7 pins also
control the byte mux. If a particular BE is HIGH during a memory read cycle, that byte is fed back to
the memory data bus. This is used during partial word write operations and writing corrected data back
to memory.
MOE
I
Memory Output Enable: when LOW, enables the output buffers of the memory data bus (MD) and
CBSYN bus. It also controls the CBSYN mux. When LOW, checkbits are selected, when HIGH,
syndrome is selected.
MDILE
I
Memory Data Input Latch Enable: on the HIGH-to-LOW transition, latches MD and CBI in MD input
latch and MD check bit latch respectively. The latches are transparent when MDILE is HIGH.
MDOLE
I
Memory Data Output Latch Enable: latches data in the MD output latch on the LOW-to-HIGH
transition of
MDOLE. When MDOLE is LOW, the MD output latch is transparent.
SDOLE
I
System Data Output Latch Enable: latches data in the SD output latch and the SD checkbit latch
on the LOW-to-HIGH transition of
SDOLE. The latch is transparent when SDOLE is LOW.
SDILE
I
System Data Input Latch Enable: latches SD in the SD input latch on the HIGH-to-LOW transition.
When SDILE is HIGH, the SD input latch is transparent.
WBSEL
I
Write FIFO Select: when HIGH, the write FIFO is selected. When WBSEL is LOW, the SD input latch
is selected.
WBEN
I
Write FIFO Enable: when LOW, allows SD data to be written to the write FIFO on the SCLK rising edge.
WBREN
I
Write FIFO Read Enable: when LOW, allows data to be read from the the write FIFO on MCLK rising
edge.
RS0-1
I
Reset and Select pins (read and write FIFO FIFOs)
RS1
RS0
Function
0
0
Reset 16-deep FIFO or first 8-deep FIFO
0
1
Reset second 8-deep FIFO
1
0
Select 16-deep FIFO or first 8-deep FIFO
1
1
Select second 8-deep FIFO
2617 tbl 01


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