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IDT49C465 Datasheet(PDF) 1 Page - Integrated Device Technology

Part No. IDT49C465
Description  32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT49C465 Datasheet(HTML) 1 Page - Integrated Device Technology

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Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AUGUST 1995
©1995 Integrated Device Technology, Inc.
11.7
DSC-9028/7
32-BIT FLOW-THRU
ERROR DETECTION
AND CORRECTION UNIT
IDT49C465
IDT49C465A
The IDT logo is a registered trademark and Flow-thruEDC is a trademarkof Integrated Device Technology Inc.
FEATURES
• 32-bit wide Flow-thruEDCunit, cascadable to 64 bits
• Single-chip 64-bit Generate Mode
• Separate system and memory buses
• On-chip pipeline latch with external control
• Supports bidirectional and common I/O memories
• Corrects all single-bit errors
• Detects all double-bit errors, some multiple-bit errors
• Error Detection Time — 12ns
• Error Correction Time — 14ns
• On chip diagnostic registers.
• Parity generation and checking on system data bus
• Low power CMOS — 100mA typical at 20MHZ
• 144-pin PGA and PQFP packages
• Military product compliant to MIL-STD 883, Class B
DESCRIPTION
The IDT49C465/A is a 32-bit, two-data bus, Flow-thruEDC
unit. The chip provides single-error correction and two and
three bit error detection of both hard and soft memory errors.
It can be expanded to 64-bit widths by cascading 2 units,
without the need for additional external logic. The Flow-
thruEDC has been optimized for speed and simplicity of
control.
The EDC unit has been designed to be used in either of two
configurations in an error correcting memory system. The
bidirectional configuration is most appropriate for systems
using bidirectional memory buses. A second system
configuration utilizes external octal buffers, and is well suited
for systems using memory with separate I/O buses.
The IDT49C465/A supports partial word writes, pipelining
and error diagnostics. It also provides parity protection for
data on the system side.
2552 drw 01
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
MD
Latch
Memory
Checkbit
Generator
Checkbit
Latch
Mux
Byte
Mux
System
Checkbit
Generator
Mux
Detect
Logic
Correct
Logic
SD
Latch
MD0–31
MLE
CBI0–7
PCBI0–7
SD0–31
SLE
PLE
CONTROL
CONTROL
CONTROL
CONTROL
CBO0–7
MERR
ERR
1


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