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IDT49C465 Datasheet(PDF) 6 Page - Integrated Device Technology

Part No. IDT49C465
Description  32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT49C465 Datasheet(HTML) 6 Page - Integrated Device Technology

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11.7
6
IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION
The error detection/correction codes consist of a modified
Hamming code; it is identical to that used in the IDT49C460.
32-BIT MODE (CODE ID 1,0=00)
Figure 5. 32-Bit Mode
VCC
CHECKBITS–IN
CHECKBITS–OUT
SYNDROME–OUT
CBO
SYO
PCBI
CBI0–6
CBI7
EDC
7
7
7
8
2552 drw 09
64-BIT MODE (CODE ID 1,0=10 & 11)
The expansion bus topology is shown in Figure 6. This
topology allows the syndrome bits used by the correction logic
to be generated simultaneously in both parts used in the
expansion. During a 64-bit detection or correction operation,
“Partial-Checkbit” data and “Partial-Syndrome” data is simul-
taneously exchanged between the two EDC units in opposite
directions on dedicated expansion buses. This results in very
short 64-bit detection and correction times.
8
8
8
8
8
FINAL
CHECKBITS–OUT
(DETECT AND CORRECT)
CBO
SYO
ERR
PCBI
CBI
UPPER EDC
PARTIAL–CHECKBITS–OUT (10)
(GENERATE ONLY)
PARTIAL–SYNDROME
(DETECT/CORRECT ONLY)
PARTIAL–CHECKBITS–OUT (10)
(GENERATE ONLY)
PARTIAL–CHECKBITS–OUT (11)
(CORRECTION ONLY)
CBO
SYO
PCBI
CBI
CHECKBITS–IN
LOWER EDC
(CODE ID 1,0 = 10)
(CODE ID 1,0 = 11)
2552 drw 10
Figure 6. 64-Bit Mode — 2 Cascaded IDT49C465 Devices
64-BIT GENERATE-ONLY MODE (CODE ID 1,0=01)
If the Identity pins CODE ID 1,0 = 01, a single EDC is placed
in the 64-bit “Generate-only” mode. In this mode, the lower 32
bits of the 64-bit data word enter the device on the MD0-31
inputs and the upper 32-bits of the 64 bit data word enter the
Figure 7. 64-Bit "Generate-Only" Mode (Single Chip)
device on the SD0-31 inputs. This provides the device with the
full 64-bit word from memory.
The resultant generated
checkbits are output on the CBO0-7 outputs. The generate
time is less than that resulting from using a 2-chip cascade.
CBO
MD0–31
SD0–31
EDC
CHECKBITS–OUT
LOWER 32 BITS (0–31)
UPPER 32 BITS (32–63)
32
32
8
2552 drw 11


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