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IDT49C465 Datasheet(PDF) 5 Page - Integrated Device Technology |
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IDT49C465 Datasheet(HTML) 5 Page - Integrated Device Technology |
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5 / 38 page  11.7 5 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES SYSTEM CONFIGURATIONS The IDT49C465 EDC unit can be used in various configurations in an EDC system. The basic configurations are shown below. Figure 1 illustrates a bidirectional configuration, which is most appropriate for systems using bidirectional memory buses. It is the simplest configuration to understand and use. During a correction cycle, the corrected data word can be simultaneously output on both the system bus and memory bus. Logically, no other parts are required for the correction function. During partial-word-write operations, the new bytes are internally combined with the corrected old bytes for checkbit generation and writing to memory. Figure 1. Common I/O Configuration Figure 2 illustrates a separate I/O configuration. This is appropriate for systems using separate I/O memory buses. This configuration allows separate input and output memory buses to be used. Corrected data is output on the SD outputs for the system and for re-write to memory. Partial word-write bytes are combined externally for writing and checkbit generation. Figure 3 illustrates a third configuration which utilizes external buffers and is also well suited for systems using memory with separate I/O buses. Since data from memory does not need to pass through the part on every cycle, the EDC system may operate in “bus-watch” mode. As in the separate I/O configuration, corrected data is output on the SD outputs. Figure 4 illustrates the single-chip generate-only mode for very fast 64-bit checkbit generation in systems that use separate checkbit-generate and detect-correct units. If this is not desired, 64-bit checkbit generation and correction can be done with just 2 EDC units. 64-bit correction is also straight- forward, fast and requires no extra hardware for the expansion. Figure 2. Separate I/O Configuration Figure 3. Bypassed Separate I/O Configuration Figure 4. Separate Generate/Correction Units with 64-Bit Checkbit Generation BUFFER MEMORY OUTPUT BUS MEMORY INPUT BUS MEMORY INPUT BUS CHECK BITS OUT CHECK BITS IN CBO 64-BIT GEN. ONLY EDC BUFFER BUFFER BUFFER CBI LOWER DATA UPPER DATA EDC EDC CPU BUS 2552 drw 08 CPU I/O MEMORY I/O CHECKBITS SD MD CBI CBO EDC 2552 drw 05 EXT.BUFFER MEMORY INPUT BUS CHECKBIT I/O MEMORY OUTPUT BUS EXT. BUFFER EXT. BUFFER CPU BUS EDC SD MD CBI CBO 2552 drw 07 CPU MEMORY INPUTS MEMORY OUTPUTS CHECKBITS CBO CBI MD SD EDC 2552 drw 06 |
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