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IDT49C465 Datasheet(PDF) 24 Page - Integrated Device Technology

Part No. IDT49C465
Description  32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT49C465 Datasheet(HTML) 24 Page - Integrated Device Technology

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24
IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
MINIMUM PULSE WIDTH
Refer to
Parameter
Minimum Pulse Width
Com’l.
Mil.
Timing Diagram
Number
Name
Input
Conditions
Min.
Min.
Unit
Figure
59
t CLEAR
Min.
CLEAR LOW time
to clear diag. registers Data = Valid
8
10
ns
14
60
t MLE
Min. MLE HIGH time
to strobe new data
MD, CBI = Valid
5
6
ns
61
t PLE
Min.
PLE LOW time
to strobe new data
SD = Valid
5
6
ns
62
t SLE
Min. SLE HIGH time
to strobe new data
SD = Valid
5
6
ns
63
t SYNCLK
Min. SYNCLK HIGH time to clock in new data
SCKEN = LOW
5
6
ns
14
2552 tbl 33
SET-UP AND HOLD TIMES - 49C465A
Parameter Description
Com.’l.
Mil.
Refer to
Parameter
From
To
Timing Diagram
Number
Name
Input
(edge)
Output
(edge)
Min.
Min.
Unit
Figure
42
t SSLS
SDIN Set-up *
before SLE = LOW
3
4
ns
7, 9
43
t SSLH
SDIN Hold
*
after SLE = LOW
3
4
ns
7, 9
44
t MMLS
MDIN Set-up *
before MLE =LOW
3
4
ns
8, 10, 11
45
t MMLH
MDIN Hold
*
after MLE = LOW
3
4
ns
8, 10, 11
46
t CMLS
CBI Set-up
*
before MLE = LOW
3
4
ns
8, 10, 11
47
t CMLH
CBI Hold
*
after MLE = LOW
3
4
ns
8, 10, 11
48
t MPLS
MDIN Set-up *
before
PLE = HIGH
10
12
ns
49
t MPLH
MDIN Hold
*
after
PLE = HIGH
0
0
ns
50
t CPLS
CBI Set-up
*
before
PLE =HIGH
10
12
ns
51
t CPLH
CBI Hold
*
after
PLE = HIGH
0
0
ns
52
t PCPLS
PCBI Set-up *
before
PLE = HIGH
10
12
ns
53
t PCPLH
PCBI Hold
*
after
PLE = HIGH
0
0
ns
DIAGNOSTIC SET-UP AND HOLD TIMES
54
t CSCS
CBI Set-up
*
10
12
ns
15
55
t MSCS
MDIN Set-up *
before SYNCLK=HIGH
10
12
ns
15
56
t MLSCS
MLE Set-up =HIGH
10
12
ns
15
57
t SESCS
SCLKEN Set-up =LOW
3
4
ns
15
58
t SESCH
SCLKEN Hold =LOW
after SYNCLK =HIGH
3
4
ns
15
NOTE:
2552 tbl 32
“*” = Where “edge” is not specified, both HIGH and LOW edges are implied.
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
1V/ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
See Figure 18
2552 tbl 34


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