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IDT49C460 Datasheet(PDF) 6 Page - Integrated Device Technology

Part No. IDT49C460
Description  32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT49C460 Datasheet(HTML) 6 Page - Integrated Device Technology

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IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
EDC ARCHITECTURE SUMMARY
The IDT49C460s are high-performance cascadable EDCs
used for check bit generation, error detection, error correction
and diagnostics. The function blocks for this 32-bit device
consist of the following:
• Data Input Latch
• Check Bit Input Latch
• Check Bit Generation Logic
• Syndrome Generation Logic
• Error Detection Logic
• Error Correction Logic
• Data Output Latch
• Diagnostic Latch
• Control Logic
DATA INPUT/OUTPUT LATCH
The Latch Enable Input, LEIN, controls the loading of 32 bits
of data to the Data In Latch. The data from the DATA lines can
be loaded in the Diagnostic Latch under control of the
Diagnostic Latch Enable, LEDIAG, giving check bit information
in one byte and control information in another byte. The
Diagnostic Latch is used in the Internal Control Mode or in one
of the diagnostic modes. The Data Output Latch has buffers
that place data on the DATA lines. These buffers are split into
four 8-bit buffers, each having their own output enable con-
trols.
This feature facilitates byte read and byte modify
operations.
CHECK BIT GENERATION LOGIC
This generates the appropriate check bits for the 32 bits of
data in the Data Input Latch. The modified Hamming Code is
the basis for generating the proper check bits.
SYNDROME GENERATION LOGIC
In both the Detect and Correct modes, this logic does a
comparison on the check bits read from memory against the
newly generated set of check bits produced for the data read
in from memory. Matching sets of check bits mean no error
was detected. If there is a mismatch, one or more of the data
or check bits is in error. Syndrome bits are produced by an
exclusive-OR of the two sets of check bits. Identical sets of
check bits mean the syndrome bits will be all zeros. If an error
results, the syndrome bits can be decoded to determine the
number of errors and the specific bit-in-error.
ERROR DETECTION LOGIC
This part of the device decodes the syndrome bits
generated by the Syndrome Generation Logic. With no errors
in either the input data or check bits, both the
ERROR and
MULTERROR outputs are HIGH. ERROR will go low if one
error is detected.
MULTERROR and ERROR will both go low
if two or more errors are detected.
ERROR CORRECTION LOGIC
In single error cases, this logic complements (corrects) the
single data bit-in-error. This corrected data is loaded into the
Data Output Latch, which can then be read onto the bidirec-
tional data lines. If the error is resulting from one of the check
bits, the correction logic does not place corrected check bits
on the syndrome/check bit outputs. If the corrected check bits
are needed, the EDC must be switched to the Generate Mode.
DATA OUTPUT LATCH AND OUTPUT BUFFERS
The Data Output Latch is used for storing the result of an
error correction operation.
The latch is loaded from the
correction logic under control of the Data Output Latch En-
able, LEOUT. The Data Output Latch may also be directly
loaded from the Data Input Latch in the PASSTHRU mode.
The Data Output Latch buffer is split into 4 individual buffers
which can be enabled by
OE0–3 separately for reading onto
the bidirectional data lines.
DIAGNOSTIC LATCH
The diagnostic latch is loadable under control of the
Diagnostic Latch Enable, LEDIAG, from the bidirectional data
lines. Check bit information is contained in one byte while the
other byte contains the control information. The Diagnostic
Latch is used for driving the device when in the Internal Control
Mode, or for supplying check bits when in one of the diagnostic
modes.
CONTROL LOGIC
Specifies in which mode the device will be operating in.
Normal operation is when the control logic is driven by external
control inputs. In the Internal Control Mode, the control signals
are read from the
Diagnostic Latch.
Since LEOUT and
GENERATE are controlled by the same pin, the latching action
(LEOUT from high to low) of the Data Output Latch causes the
EDC to go into the Generate Mode.


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