MK2771-13

VCXO and Set-Top Clock Source

MDS 2771-13 A

2

Revision 110298

Printed 11/16/00

Integrated Circuit Systems • 525 Race Street•San Jose•CA•95126•(408)295-9800tel•www.icst.com

Pin Descriptions

Key: I = Input, TI = Tri-level input, O = output, P = power supply connection

Pin Assignment

Number

Name

Type

Description

1

PCS0

I

Processor Clock Select 0. Selects PCLK on pin 8. See table above.

2

X2

XO

Crystal connection. Connect to a pullable 13.5 MHz crystal.

3

X1

XI

Crystal connection. Connect to a pullable 13.5 MHz crystal.

4, 6, 15

VDD

P

Connect to +5V.

5

VIN

I

Voltage Input to VCXO. Zero to 3V signal which controls the frequency of the VCXO.

7, 14, 17

GND

P

Connect to ground.

8

PCLK

O

Processor clock output determined by status of PCS1,0. See table above.

9

BCLK

O

33.33MHz or 24.576 MHz Bus Clock output. See table above.

10

ACLK

O

Audio clock output determined by status of ACS1,0. See table above.

11

13.5M

O

13.5 MHz clock output. Divide by two of the 27MHz VCXO output.

12

PCS1

TI

Processor Clock Select 1. Selects PCLK on pin 8. See table above.

13

27M

O

27.00 MHz VCXO clock output.

16

27M

O

27.00 MHz VCXO clock output.

18

BCS

P

Bus Clock Select . Selects BCLK on pin 9. See table above.

19

ACS0

I

Audio Clock Select 0. Selects ACLK on pin 10. See table above.

20

ACS1

I

Audio Clock Select 1. Selects ACLK on pin 10. See table above.

1

16

2

3

4

15

14

13

VDD

GND

X2

VDD

GND

5

6

7

8

12

11

10

9

BCLK

ACS0

X1

PCS0

27M

27M

13.5M

ACLK

PCLK

PCS1

PCS0

PCLK (MHz)

0

0

50.000

0

1

16.667

M

0

25.000

M

1

32.000

1

0

40.000

1

1

20.000

18

17

19

20

VIN

VDD

PCS1

GND

Processor Clock Select Table

Audio Clock Table

0 = connect directly to ground, 1 = connect directly

to VDD, M = leave floating or unconnected

ACS1 ACS0 ACLK (MHz)

0

0

8.192

0

1

11.2896

1

0

12.288

1

1

5.6448

BCS

ACS1

BCS

BCLK (MHz)

0

33.333

1

24.576

Bus Clock Table