MK2049-35

3.3 V Communications Clock PLL

MDS 2049-35 A

2

Revision 121300

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com

Pin Descriptions

Type: XI, XO = crystal connections, I = Input, O = output, P = power supply connection, LF = loop filter

connections

Pin Assignment

20 pin (300 mil) SOIC

1

16

2

3

4

15

14

13

VDD

GND

X2

VDD

GND

5

6

7

8

12

11

10

9

FS3

X1

FS1

FS0

CAP1

ICLK

8K

CLK/2

CLK

18

17

19

20

FCAP

VDD

FS2

GND

CAP2

RES

Number

Name

Type Description

1

FS1

I

Frequency Select 1. Determines CLK input/outputs per tables on page 4.

2

X2

XO Crystal connection. Connect to a MHz crystal as shown in the tables on page 4.

3

X1

XI

Crystal connection. Connect to a MHz crystal as shown in the tables on page 4.

4

VDD

P

Connect to +3.3V.

5

FCAP

-

Filter Capacitor. Connect a 1000 pF ceramic capacitor to ground.

6

VDD

P

Connect to +3.3V.

7

GND

P

Connect to ground.

8

CLK

O

Clock output determined by status of FS3:0 per tables on page 4.

9

CLK/2

O

Clock output determined by status of FS3:0 per tables on page 4. Always 1/2 of CLK.

10

8K

O

Recovered 8 kHz clock output.

11

FS2

I

Frequency Select 2. Determines CLK input/outputs per tables on page 4.

12

FS3

I

Frequency Select 3. Determines CLK input/outputs per tables on page 4.

13

ICLK

I

Input clock connection. Connect to 8 kHz backplane or MHz clock.

14

GND

P

Connect to ground.

15

VDD

P

Connect to +3.3V.

16

CAP1

LF

Connect the loop filter ceramic capacitors and resistor between this pin and CAP2.

17

GND

P

Connect to ground.

18

CAP2

LF

Connect the loop filter ceramic capacitors and resistor between this pin and CAP1.

19

RES

-

Connect a 10-200k

Ω resistor to ground. Contact ICS applications dept. at 408-297-1201 for the recommended value for your app.

20

FS0

I

Frequency Select 0. Determines CLK input/outputs per tables on page 4.