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AD9712B Datasheet(PDF) 5 Page - Analog Devices |
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AD9712B Datasheet(HTML) 5 Page - Analog Devices |
5 / 12 page OBSOLETE AD9712B/AD9713B REV. B –5– DIE LAYOUT AND METALIZATION INFORMATION Die Dimensions . . . . . . . . . . . . . . . . . 220 × 196 × 15 (±2) mils Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 × 4 mils Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –VS Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nitride THEORY AND APPLICATIONS The AD9712B and AD9713B high speed digital-to-analog converters utilize Most Significant Bit (MSB) decoding and segmentation techniques to reduce glitch impulse and main- tain 12-bit linearity without trimming. As shown in the functional block diagram, the design is based on four main subsections: the Decoder/Driver circuits, the Transparent Latches, the Switch Network, and the Control Am- plifier. An internal bandgap reference is also included to allow operation with a minimum of external components. Digital Inputs/Timing The AD9712B employs single-ended ECL-compatible inputs for data inputs D1–D12 and LATCH ENABLE. The internal ECL midpoint reference is designed to match 10K ECL device thresholds. On the AD9713B, a TTL translator is added at each input; with this exception, the AD9712B and AD9713B are identical. In the Decoder/Driver section, the four MSBs (D1–D4) are decoded to 15 “thermometer code” lines. An equalizing delay is included for the eight Least Significant Bits (LSBs) and LATCH ENABLE. This delay minimizes data skew, and data setup and hold times at the latch inputs; this is important when operating the latches in the transparent mode. Without the delay, skew caused by the decoding circuits would degrade glitch impulse. The latches operate in their transparent mode when LATCH ENABLE (Pin 26) is at logic level “0.” The latches should be used to synchronize data to the current switches by applying a narrow LATCH ENABLE pulse with proper data setup and hold times as shown in the Timing Diagram. An external latch at each data input, clocked out of phase with the Latch Enable, operates the AD9712B/AD9713B in a master slave (edge- triggered) mode. This is the optimum way to operate the DAC because data is always stable at the DAC input. An external latch eases timing constraints when using the converter. Although the AD9712B/AD9713B chip is designed to provide isolation from digital inputs to the outputs, some coupling of digital transitions is inevitable, especially with TTL or CMOS inputs applied to the AD9713B. Digital feedthrough can be re- duced by forming a low-pass filter using a (200 Ω) series resistor in series with the capacitance of each digital input; this rolls off the slew rate of the digital inputs. References As shown in the functional block diagram, the internal bandgap reference, control amplifier, and reference input are pinned out for maximum user flexibility when setting the reference. When using the internal reference, REFERENCE OUT (Pin 20) should be connected to CONTROL AMP IN (Pin 19). CON- TROL AMP OUT (Pin 18) should be connected to REFER- ENCE IN (Pin 17) through a 20 Ω resistor. A 0.1 µF ceramic capacitor from Pin 17 to –VS (Pin 15) improves settling by decoupling switching noise from the current sink base line. A reference current cell provides feedback to the control amp by sinking current through RSET (Pin 24). tS – INPUT SETUP TIME t LPW – LATCH PULSE WIDTH – OUTPUT PROPAGATION DELAY t PD t H – INPUT HOLD TIME t ST – OUTPUT SETTLING TIME OUTPUT ERROR ERROR BAND t PD LATCH ENABLE tST t LPW t S t H VALID DATA t PD DATA INPUTS OUTPUT LATCH ENABLE Timing Diagram |
Similar Part No. - AD9712B_15 |
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Similar Description - AD9712B_15 |
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