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ICSSSTV16857 Datasheet(PDF) 6 Page - Integrated Circuit Systems |
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ICSSSTV16857 Datasheet(HTML) 6 Page - Integrated Circuit Systems |
6 / 8 page 6 ICSSSTV16857 Third party brands and names are the property of their respective owners. Notes: 1. CL incluces probe and jig capacitance. 2. IDD tested with clock and data inputs held at VDD or GND, and Io = 0mA. 3. All input pulses are supplied by generators having the following chareacteristics: PRR ≤10 MHz, Zo=50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified). 4. The outputs are measured one at a time with one transition per measurement. 5. VTT = VREF = VDDQ/2 6. VIH = VREF + 310mV (ac voltage levels) for differential inputs. VIH = VDD for LVCMOS input. 7. VIL = VREF -310mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input. 8. tPLH and tPHL are the same as tpd Test Point Load Circuit From Output Under Test C = 30 pF (see Note 1) L VTT R = L 50W LVCMOS RESET# Input LVCMOS RESET# Input V/2 DD tinact tact I (see note 2) DD IDDH IDDL 10% 90% Voltage and Current Waveforms Inputs Active and Inactive Times Voltage Waveforms - Propagation Delay Times Voltage Waveforms - Propagation Delay Times Parameter Measurement Information (V = 2.5V ±0.2V) DD Voltage Waveforms - Pulse Duration Voltage Waveforms - Setup and Hold Times V/2 DD VDD 0V tw tSU th VIH VIH VOH VTT VTT VTT VOH VIH VIL VIL VOL VOL VI(pp) VI(pp) VIL VREF VREF VREF VREF VICR VICR tPHL tPHL tPHL V/2 DD VICR Input Input Timing Input Timing Input Output Output |
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