4

ICS9250-32

Third party brands and names are the property of their respective owners.

Byte 0: Active/Inactive Control Register

(1= enable, 0 = disable)

Byte 1: Active/Inactive Control Register

(1= enable, 0 = disable)

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B0

31

7

M

A

R

D

S

6

t

i

B1

31

6

M

A

R

D

S

5

t

i

B4

31

5

M

A

R

D

S

4

t

i

B5

31

4

M

A

R

D

S

3

t

i

B8

31

3

M

A

R

D

S

2

t

i

B9

31

2

M

A

R

D

S

1

t

i

B0

41

1

M

A

R

D

S

0

t

i

B3

41

0

M

A

R

D

S

Notes:

1. Inactive means outputs are held LOW and are disabled

from switching.

2. Latched Frequency Selects (FS#) will be inverted logic

load of the input frequency select pin conditions.

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B-

0

d

e

v

r

e

s

e

R

6

t

i

B-

>

<d

e

v

r

e

s

e

R

5

t

i

B-

>

<d

e

v

r

e

s

e

R

4

t

i

B-

>

<d

e

v

r

e

s

e

R

3

t

i

B-

0

d

e

v

r

e

s

e

R

2

t

i

B-

0

d

e

v

r

e

s

e

R

1

t

i

B-

0

d

e

v

r

e

s

e

R

0

t

i

B-

0

d

e

v

r

e

s

e

R

Byte 3: Active/Inactive Control Register

(1= enable, 0 = disable)

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B-

0

d

e

v

r

e

s

e

R

6

t

i

B-

0

d

e

v

r

e

s

e

R

5

t

i

B-

0

d

e

v

r

e

s

e

R

4

t

i

B-

0

d

e

v

r

e

s

e

R

3

t

i

B-

0

d

e

v

r

e

s

e

R

2

t

i

B-

0

d

e

v

r

e

s

e

R

1

t

i

B-

0

d

e

v

r

e

s

e

R

0

t

i

B-

0

d

e

v

r

e

s

e

R

Byte 4: Active/Inactive Control Register

(1= enable, 0 = disable)

Byte 2: Active/Inactive Control Register

(1= enable, 0 = disable)

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B2

21

7

K

L

C

I

C

P

6

t

i

B1

21

6

K

L

C

I

C

P

5

t

i

B8

11

5

K

L

C

I

C

P

4

t

i

B7

11

4

K

L

C

I

C

P

3

t

i

B6

11

3

K

L

C

I

C

P

2

t

i

B5

11

2

K

L

C

I

C

P

1

t

i

B2

11

1

K

L

C

I

C

P

0

t

i

B1

11

0

K

L

C

I

C

P

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B-

0

d

e

v

r

e

s

e

R

6

t

i

B-

0

d

e

v

r

e

s

e

R

5

t

i

B-

0

d

e

v

r

e

s

e

R

4

t

i

B-

0

d

e

v

r

e

s

e

R

3

t

i

B-

0

m

u

r

t

c

e

p

S

d

a

e

r

p

S

f

f

O

=

1

/

n

O

=

0

(

2

t

i

B1

1

)

T

O

D

(

M

8

4

V

2

1

t

i

B2

1

)

B

S

U

(

M

8

4

V

3

0

t

i

B-

1

d

e

v

r

e

s

e

R

Note:

<>, with these 3 bits, the registers will store the written

values. The read back, however, will be the invert of the

written value.