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ICS9250-29 Datasheet(PDF) 8 Page - Integrated Circuit Systems

Part # ICS9250-29
Description  Frequency Generator & Integrated Buffers for Celeron & PII/III?
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Manufacturer  ICST [Integrated Circuit Systems]
Direct Link  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS9250-29 Datasheet(HTML) 8 Page - Integrated Circuit Systems

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ICS9250-29
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections
of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A = 0 - 70C; Supply Voltage VDD = 3.3 V +5%, VDDL=2.5 V+ 5%(unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
V
IH
2V
DD+0.3
V
Input Low Voltage
V
IL
V
SS-0.3
0.8
V
Input High Current
I
IH
V
IN = VDD
-5
5
µA
Input Low Current
I
IL1
V
IN = 0 V; Inputs with no pull-up resistors
-5
µA
Input Low Current
I
IL2
V
IN = 0 V; Inputs with pull-up resistors
-200
µA
Operating
I
DD3.3OP
C
L = 0 pF; Select @ 66M
100
mA
Supply Current
Power Down
I
DD3.3PD
C
L = 0 pF; With input address to Vdd or GND
600
µA
Supply Current
Input frequency
F
i
V
DD = 3.3 V;
14.318
MHz
Pin Inductance1
L
pin
7nH
C
IN
Logic Inputs
5
pF
C
out
Out put pin capacitance
6
pF
C
INX
X1 & X2 pins
13.5
22.5
pF
Transition Time1
T
trans
To 1st crossing of target Freq.
3
ms
Settling Time1
T
s
From 1st crossing to 1% target Freq.
3
ms
Clk Stabilization1
T
STAB
From V
DD = 3.3 V to 1% target Freq.
3
ms
t
PZH,tPZH
output enable delay (all outputs)
1
10
ms
t
PLZ,tPZH
output disable delay (all outputs)
1
10
ms
1Guarenteed by design, not 100% tested in production.
Delay1
Input Capacitance1
Group Timing Relationship Table
1
p
u
o
r
Gz
H
M
6
6
U
P
C
z
H
M
0
0
1
M
A
R
D
S
z
H
M
0
0
1
U
P
C
z
H
M
0
0
1
M
A
R
D
S
z
H
M
3
3
1
U
P
C
z
H
M
0
0
1
M
A
R
D
S
z
H
M
3
3
1
U
P
C
z
H
M
3
3
1
M
A
R
D
S
t
e
s
f
f
Oe
c
n
a
r
e
l
o
Tt
e
s
f
f
Oe
c
n
a
r
e
l
o
Tt
e
s
f
f
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n
a
r
e
l
o
Tt
e
s
f
f
Oe
c
n
a
r
e
l
o
T
M
A
R
D
S
o
t
U
P
Cs
n
5
.
2
-s
p
0
0
5s
n
0
.
5s
p
0
0
5s
n
0
.
0s
p
0
0
5s
n
5
7
.
3s
p
0
0
5
6
6
V
3
o
t
U
P
Cs
n
5
.
7s
p
0
0
5s
n
0
.
5s
p
0
0
5s
n
0
.
0s
p
0
0
5s
n
0
.
0s
p
0
0
5
6
6
V
3
o
t
M
A
R
D
Ss
n
0
.
0s
p
0
0
5s
n
0
.
0s
p
0
0
5s
n
0
.
0s
p
0
0
5s
n
5
7
.
3
-s
p
0
0
5
I
C
P
o
t
6
6
V
3s
n
5
.
3
-
5
.
1s
p
0
0
5s
n
5
.
3
-
5
.
1s
p
0
0
5s
n
5
.
3
-
5
.
1s
p
0
0
5s
n
5
.
3
-
5
.
1s
p
0
0
5
C
I
P
A
O
I
o
t
I
C
Ps
n
0
.
0s
n
1s
n
0
.
0s
n
1s
n
0
.
0s
n
1s
n
0
.
0s
n
1
T
O
D
&
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S
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AA
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