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ICS9248YF-96-T Datasheet(PDF) 2 Page - Integrated Circuit Systems |
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ICS9248YF-96-T Datasheet(HTML) 2 Page - Integrated Circuit Systems |
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2 / 12 page  2 ICS9248-96 0311D—04/23/04 General Description Pin Configuration PIN NUMBER PIN NAME TYPE DESCRIPTION FREQ_IOAPIC IN If FREQ_APIC = 0, APIC Clock = PCICLK If FREQ_APIC = 1, APIC Clock = PCICLK/2 (default) REF0 OUT 14.318 MHz reference clock. 2, 9, 10, 18, 25, 30, 38 VDD PWR 3.3V Power supply for SDRAM output buffers, PCI output buffers, reference output buffers and 48MHz output 3 X1 IN Crystal input,nominally 14.318MHz. 4 X2 OUT Crystal output, nominally 14.318MHz. 5, 6, 14, 21, 29, 34, 42 GND PWR Ground pin for 3V outputs. 8, 7 3V66 [1:0] OUT 3.3V Clocks FS0 IN Frequency select pin. PCICLK0 OUT PCI clock output FS1 IN Frequency select pin. PCICLK1 OUT PCI clock output SEL24_48MHz# IN Logic inputs frequency select I/O/USB output, When a "0" is latched, output frequency = 48MHz When a "1" is latched, output frequency = 24MHz PCICLK2 OUT PCI clock output 20, 19, 17, 16, 15 PCICLK [7:3] OUT PCI clock outputs. 22 PD# IN Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. 23 SCLK IN Clock input of I2C input, 5V tolerant input 24 SDATA IN Data input for I2C serial input, 5V tolerant input FS3 IN Frequency select pin. 48MHz_0 OUT 48MHz output clocks 27 48MHz_1 OUT 48MHz output clocks FS2 IN Frequency select pin. 24_48MHz OUT 24 or 48MHz output 31 SDRAM_F OUT Free running SDRAM - used for feed back to chipset, should remain on always. 32, 33, 35, 36, 37, 39, 40, 41, SDRAM [7:0] OUT SDRAM clock outputs 43 GNDLCPU PWR Ground pin for the CPU clocks. 44, 45 CPUCLK [1:0] OUT CPU clock outputs. 46 VDDLCPU PWR Power pin for the CPUCLKs. 2.5V 47 IOAPIC OUT 2.5V clock output 48 VDDLAPIC PWR Power pin for the IOAPIC. 2.5V 1 26 28 11 12 13 Power Groups GNDREF, VDDREF = REF0, X1, X2 GNDPCI , VDDPCI = PCICLK [9:0] GNDSDR, VDDSDR = SDRAM [7:0], SDRAM_F, supply for PLL core GND3V66 , VDD3V66 = 3V66 GND48 , VDD48 = 48MHz, 24_48MHz, VDDLAPIC = IOAPIC GNDLCPU , VDDLCPU = CPUCLK [1:0] ICS9248-96 is the single chip clock solution for designs using the 810/810E style chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I 2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding.The ICS9248- 96 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Serial programming I 2C interface allows changing functions, stop clock programming and frequency selection. |
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