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ICS9248-65 Datasheet(PDF) 3 Page - Integrated Circuit Systems |
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ICS9248-65 Datasheet(HTML) 3 Page - Integrated Circuit Systems |
3 / 10 page 3 ICS9248-65 Frequency Select: Note: 1. TCLK is a test clock driven on the x1 input during test mode. ICS9248-65 Power Management Features: Note: 1. LOW means outputs held static LOW as per latency requirement next page. 2. On means active. 3. PD# pulled Low, impacts all outputs including REF and 48 MHz outputs. L E S # 0 0 1 / 3 3 1 1 L E S0 L E S U P C z H M 2 / U P C z H M 6 6 V 3 z H M I C P z H M 8 4 z H M F E R z H M C I P A O I z H M s t n e m m o C 00 0 Z - i HZ - i HZ - i HZ - i HZ - i HZ - i HZ - i He t a t s - i r T 00 1 A / NA / NA / NA / NA / NA / NA / Nd e v r e s e R 01 0 0 0 10 56 . 6 63 . 3 3Z - i H8 1 3 . 4 17 6 . 6 1 L L P z H M 8 4 d e l b a s i d 01 1 0 0 10 56 . 6 63 . 3 38 48 1 3 . 4 17 6 . 6 1 10 0 2 / K L C T4 / K L C T4 / K L C T8 / K L C T2 / K L C TK L C T6 1 / K L C T) 1 ( e d o m t s e T 10 1 A / NA / NA / NA / NA / NA / NA / Nd e v r e s e R 11 0 3 . 3 3 16 66 63 3Z - i H8 1 3 . 4 17 6 . 6 1 11 1 3 . 3 3 16 66 63 38 48 1 3 . 4 17 6 . 6 1 # D PK L C U P C2 / U P CC I P A O I6 6 V 3I C PF _ I C P . F E R z H M 8 4 c s Os O C V 0W O LW O LW O LW O LW O LW O LW O LF F OF F O 1N ON ON ON ON ON ON ON ON O Power Management Requirements: Note: 1. Clock on/off latency is defined in the number of rising edges of free running PCICLKs between the clock disable goes low/ high to the first valid clock comes out of the device. 2. Power up latency is when PWR_DWN# goes inactive (high to when the first valid clocks are dirven from the device. l a g n i Se t a t S l a g n i S y c n e t a L s e g d e g n i si r f o . o N K L C I C P f o # D P ) n o it a r e p o l a m r o n ( 1S m 3 ) n w o d r e w o p ( 0. x a m 2 |
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