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ICS9150F-04 Datasheet(PDF) 1 Page - Integrated Circuit Systems |
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ICS9150F-04 Datasheet(HTML) 1 Page - Integrated Circuit Systems |
1 / 19 page Integrated Circuit Systems, Inc. General Description Features ICS9150- 04 Block Diagram Pentium is a trademark of Intel Corporation I 2C is a trademark of Philips Corporation. Pentium Pro™ and SDRAM Frequency Generator 9150-04 RevD 07/27/98 Pin Configuration Generates five processor, six bus, one 14.31818MHz (3.3V) three IOAPIC, 16 SDRAM clocks, 48MHz USB clock and 24MHz Super I/O clock. Synchronous clocks skew matched to 250 ps window on CPUCLKs and 500ps window on PCICLKs Skew from CPU (earlier) to PCI clock - 1 to 4ns, 2.6ns nom. Power Management Control Input pins when MODE Low VDD(1:4) - 3.3V ±10% (inputs 5V tolerant w/series R ) VDDL(1:2) - 2.5V or 3.3V ±5% I2C interface for programming stopclocks plus spread spectrum options (±0.5% or ±1.5%, center spread or down spread) 56-pin SSOP package 56-Pin SSOP The ICS9150-04 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro or Cyrix. Eight different reference frequency multiplying factors are selectable from 50 to 83.3MHz. Features include five CPU, seven PCI and Sixteen SDRAM clocks. One reference output is available equal to the crystal frequency, plus three IOAPIC outputs powered by VDDL1. One 48 MHz for USB is provided plus a 24 MHz. Spread Spectrum built in up to ±1.5% modulation to reduce EMI. Serial programming I2C interface allows changing functions, stop clock programing and Frequency selection. Rise time adjustment for VDD at 3.3V or 2.5V CPU. Additionally, the device meets the Pentium power-up stabilization, which requires that CPU and PCI clocks be stable within 2ms after power-up. High drive PCICLK and SDRAM outputs typically provide greater than 1 V/ns slew rate into 30pF loads. CPUCLK outputs typically provide better than 1V/ns slew rate into 20pF loads while maintaining 50±5% duty cycle. The REF 24 and 48 MHz and SDRAM 12, 13 clock outputs typically provide better than 0.5V/ns slew rates. Power Groups VDD1 = REF, X1, X2 VDD2 = PCICLK_F, PCICLK(0:5) VDD3 = SDRAM (0:15), supply for PLL core, VDD4 = 48MHz, 24MHz VDDL1 = IOAPIC (0:2) VDDL2 = CPUCLK (0:4) ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. |
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