4

ICS9148- 58

Byte0: Functionality and Frequency Select Register

(default = 0)

Serial Configuration Command Bitmap

Bit

Description

PWD

Bit 7 Reserved

0

Bit

6:4

Bit6 Bit5

Bit4

111

110

101

100

011

010

001

000

CPU Clock

100.2

95.25

83.3

133.3

75

124

66.8

112

PCI

33.3

31.75

33.3

44.3

37.5

41.3

33.4

37.3

AGP

66.6

63.5

66.6

88.7

75

82.7

66.8

74.7

Note

1

Bit 3

0 - Frequency is selected by hardware select,

Latched Inputs

1 - Frequency is selected by Bit 6:4 (above)

0

Bit 2

0 - Spread Spectrum center spread type. ±.25%

1 - Spread Spectrum down spread type. 0 to -.5%

0

Bit 1 0 - Normal

1 - Spread Spectrum Enabled

0

Bit 0

0 - Running

1- Tristate all outputs

0

General I

programming application note.

How to Write:

and byte count.

See the diagram below:

Note that the acknowledge bit is sent by the clock chip, and pulls the data line low. There is no minimum of data bytes that must

be sent.

How to Read:

See the diagram below:

The following specifications should be observed:

1.

2.

Maximum data transfer rate (SCLK) is 100K bits/sec.

Clock Generator

Address (7 bits)

ACK

+ 8 bits

dummy

command code

ACK

+ 8 bits

dummy Byte

count

ACK

Data Byte

1

ACK

Data Byte

N

ACK

A(6:0) & R/W#

Clock Generator

Address (7 bits)

ACK

Byte

C ount

ACK

Data Byte

1

AC K

Data Byte

N

A(6:0) & R/W#

Note 1. Default at Power-up will be for latched logic inputs

to define frequency. Bits 4, 5, 6 are default to 000,

and if bit 3 is written to a 1 to use Bits 6:4, then

these should be defined to desired frequency at same

write cycle.

Note: PWD = Power-Up Default