2

ICS9148-18

Pin Descriptions

Select Functions

(Functionality determined by FS0 and SEL100/66# pin, see below)

Notes:

1. TCLK is a test clock driven on the X1 (crystal in pin) input during test mode.

PIN NUMBER

PIN NAME

TYPE

DESCRIPTION

26

REF0

OUT

14.318MHz clock output

28

GND1

PWR

Ground for REF outputs

1X1

IN

XTAL_IN 14.318MHz Crystal input, has internal 33pF load

cap and feed back resistor from X2

2

X2

OUT

XTAL_OUT Crystal output, has internal load cap 33pF

3, 12

GND2

PWR

Ground for PCI outputs

4

PCICLK_F

OUT

Free Running PCI output

5, 7, 8, 10, 11

PCICLK (0:4)

OUT

PCI clock outputs. TTL compatible 3.3V

6, 9

VDD2

PWR

Power for PCICLK outputs, nominally 3.3V

13, 21

VDD

PWR

Isolated power for core, nominally 3.3V

14, 20

GND

PWR

Isolated ground for core

15

SEL100/66.6#

IN

Select pin for enabling 100MHz or 66.6MHz

H=100MHz, L=66.6MHz (PCI always synchronous 33.3MHz)

16

FS0

IN

Frequency Select pin

17

PD#

IN

Powers down chip, active low

18

CPU_STOP#

IN

Halts CPU clocks at logic "0" level when low

19

PCI_STOP#

IN

Halts PCI Bus at logic "0" level when low

25

VDDL

PWR

Power for CPU outputs, nominally 2.5V

22

GNDL

PWR

Ground for CPU outputs.

23, 24

CPUCLK (1:0)

OUT

CPU and Host clock outputs @ 2.5V

27

VDD1

PWR

Power for REF outputs.

Functionality

CPUCLK

PCI,

PCI_F

REF0

Tristate

HI - Z

HI - Z

HI - Z

Testmode

TCLK/2

1

TCLK/6

1

TCLK

1

SEL 100/66#

FS0

Function

00

Tri-State

0

-

(Reserved)

0

-

(Reserved)

0

1

Active 66.6MHz CPU, 33.3 PCI

10

Test Mode

1

-

(Reserved)

1

-

(Reserved)

1

1

Active 100MHz CPU, 33.3 PCI