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ICS8533AG-01 Datasheet(PDF) 8 Page - Integrated Circuit Systems |
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ICS8533AG-01 Datasheet(HTML) 8 Page - Integrated Circuit Systems |
8 / 13 page 8533AG-01 www.icst.com/products/hiperclocks.html REV. B JULY 16, 2001 8 Integrated Circuit Systems, Inc. ICS8533-01 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS R2 1K V CC CLK_IN + - R1 1K C1 0.1uF V_REF R2 1K V CC CLK_IN + - R1 1K C1 0.1uF V_REF FIGURE 8: SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT Figure 8 shows how the differential input can be wired to accept single end levels. The reference voltage V_REF ~ V CC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and V CC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. |
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