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ICS674R-01IT Datasheet(PDF) 4 Page - Integrated Circuit Systems |
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ICS674R-01IT Datasheet(HTML) 4 Page - Integrated Circuit Systems |
4 / 6 page ICS674-01 User Configurable Divider MDS 674-01 A 4 Revision 033199 Printed 11/15/00 Integrated Circuit Systems • 525 Race Street • San Jose • CA • 95126 •(408)295-9800tel•(408)295-9818fax PRELIMINARY INFORMATION Output Clock Divide A REFIN FBIN ICS673-01 CLK1 CLK2 Divide B Post Divide Reference Clock If the reference is in the kHz range, for example 8 kHz, the following configuration may be more typical: Output Clock Divide A REFIN FBIN ICS673-01 CLK1 CLK2 Divide B Post Divide Reference Clock Note that in both examples Divide B is connected to the output of the ICS673. This is because Divide B has a higher operating frequency than Divide A. Using the ICS674-01 with the ICS673-01: The ICS674-01 may be used with the ICS673-01 to build a frequency synthesizer. The following example shows a typical application when the reference clock is in the MHz range: ICS674-01 ICS674-01 |
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