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ICS82C404M Datasheet(PDF) 5 Page - Integrated Circuit Systems |
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ICS82C404M Datasheet(HTML) 5 Page - Integrated Circuit Systems |
5 / 13 page Serial Programming Architecture The pins SEL0 and SEL1 perform the dual functions of select- ing registers and serial programming. In serial programming mode, SEL0 acts as a clock pin while SEL1 acts as the data pin. The ICS82C404-01 may not be serially programmed when in power-down mode. In order to program a particular register, an unlocking sequence must occur. The unlocking sequence is detailed in the following timing diagram: The unlock sequence consists of at least five low-to-high transitions of CLK while data is high, followed immediately by a single low-to-high transition while data is low. Following this unlock sequence, data can be loaded into the serial data register. Following any transition of CLK or DATA, the watchdog timer is reset and begins counting. The watchdog timer ensures that successive rising edges of CLK and DATA do not violate the time-out specification of 2ms. If a time-out occurs, the lock mechanism is reset and the data in the serial data register is ignored. Figure 1: Serial Data Timing Since the VCLK registers are selected by the SEL0 and SEL1 pins, and since any change in their state may affect the output frequency, new data input on the selection bits is only permitted to pass through the decode logic after the watchdog timer has timed out. This delay of SEL0 or SEL1 data permits a serial program cycle to occur without affecting the current register selection. Serial Data Register The serial data is clocked into the serial data register in the order described in Figure 1 below (Serial Data Timing). The serial data is sent as follows: An individual data bit is sampled on the rising edge of CLK. The complement of the data bit must be sampled on the previous falling edge of CLK. The set-up and hold time requirements must be met on both CLK edges. For specifics on timing, see the timing diagrams on pages 10, 11 and 12. The bits are shifted in this order: a start bit, 21 data bits, 3 address bits (which designate the desired register), and a stop bit. A total of 24 bits must always be loaded into the serial data register or an error is issued. Following the entry of the last data bit, a stop bit or load command is issued by bringing DATA high and toggling CLK high-to-low and low-to-high. The unlocking mechanism then resets itself following the load. Only after a time-out period are the SEL0 and SEL1 pins allowed to return to a register selection function. ICS82C404 5 |
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