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ICS671M-01 Datasheet(PDF) 3 Page - Integrated Circuit Systems |
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ICS671M-01 Datasheet(HTML) 3 Page - Integrated Circuit Systems |
3 / 4 page ICS671-01 Zero Delay, Low Skew Buffer and Multipler MDS 671-01 B 3 Revision 051700 Printed 11/15/00 Integrated Circuit Systems, Inc.• 525 Race Street • San Jose •CA•95126• (408) 295-9800 tel • www.icst.com Parameter Conditions Minimum Typical Maximum Units ABSOLUTE MAXIMUM RATINGS (n note 1) Supply voltage, VDD Referenced to GND -0.5 7 V Inputs and Clock Outputs Referenced to GND -0.5 VDD+0.5 V Electrostatic Discharge MIL-STD-883 2000 V Ambient Operating Temperature 0 70 °C Soldering Temperature Max of 10 seconds 260 °C Junction temperature 150 °C Storage temperature -65 150 °C DC CHARACTERISTICS (VDD = 3.3 V unless specified ottherwise) Operating Voltage, VDD 3.13 5.50 V Input High Voltage, VIH, CLKIN pin only VDD/2+1 VDD/2 V Input Low Voltage, VIL, CLKIN pin only VDD/2 VDD/2-1 V Input High Voltage, VIH 2 V Input Low Voltage, VIL 0.8 V Output High Voltage, VOH IOH=-25mA 2.4 V Output Low Voltage, VOL IOL=25mA 0.4 V Output High Voltage, VOH, CMOS level IOH=-8mA VDD-0.4 V Operating Suppl Current, IDD (Note 2) No Load, S1=1, S0=0 25 mA Operating Suppl Current, IDD (Note 3) No Load, S1=1, S0=0 74 mA Short Circuit Current Each output ±50 mA Input Capacitance S0, S1, FBIN 7 pF AC CHARACTERISTICS (VDD = 3.3 V unless specified oth herwise) Input Clock Frequency See table on page 2 5 80 MHz Output Clock Frequency See table on page 2 5 160 MHz Output Clock Rise Time, CL=30pF 0.8 to 2.0V 1.5 ns Output Clock Fall Time, CL=30pF 2.0 to 0.8V 1.5 ns Output Clock Duty Cycle, VDD=3.3V At VDD/2 40 50 60 % Device to Device Skew, equally loaded rising edges at VDD/2 700 ps Output to Output Skew, equally loaded rising edges at VDD/2 250 ps Input to Output Skew, FBIN to CLK8 rising edges at VDD/2 ±350 ps Maximum Absolute Jitter 300 ps Cycle to Cycle Jitter, 30pF loads 500 ps Electrical Specifications Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability. 2. With CLKIN = 20 MHz, FBIN to CLK8, all outputs at 40 MHz. 3. With CLKIN = 80 MHz, FBIN to CLK8, all outputs at 160 MHz. |
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