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ICS650R-07 Datasheet(PDF) 4 Page - Integrated Circuit Systems |
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ICS650R-07 Datasheet(HTML) 4 Page - Integrated Circuit Systems |
4 / 5 page ICS650-07C Networking Clock Source MDS 650-07C A 4 Revision 101399 Printed 11/28/00 Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel • www.icst.com PRELIMINARY INFORMATION Parameter Conditions Minimum Typical Maximum Units ABSOLUTE MAXIMUM RATINGS (note 1) ABSOLUTE MAXIMUM RATINGS (note 1) Supply voltage, VDD Referenced to GND 7 V Inputs and Clock Outputs Referenced to GND -0.5 VDD+0.5 V Ambient Operating Temperature 0 70 °C Ambient Operating Temperature, I version Industrial temp -40 85 °C Soldering Temperature Max of 20 seconds 260 °C Storage temperature -65 150 °C DC CHARACTERISTICS (VDD = 5.0V unless noted) DC CHARACTERISTICS (VDD = 5.0V unless noted) Operating Voltage, VDD 3 5.5 V Input High Voltage, VIH, X1 pin only Clock input VDD/2 + 1 VDD/2 V Input Low Voltage, VIL, X1 pin only Clock input VDD/2 VDD/2 - 1 V Input High Voltage, VIH, all TI type inputs VDD-0.5 V Input Low Voltage, VIL, all TI type inputs 0.5 V Input High Voltage, VIH, all I type inputs 2 V Input Low Voltage, VIL, all I type inputs 0.8 V Output High Voltage, VOH IOH=-25mA 2.4 V Output Low Voltage, VOL IOL=25mA 0.4 V Output High Voltage, VOH, CMOS level IOH=-8mA VDD-0.4 V Operating Supply Current, IDD No Load 60 mA Short Circuit Current Each output ±100 mA Internal pull-up resistor ACS1, BCS1, OE 200 k Ω AC CHARACTERISTICS (VDD = 5.0V unless noted) AC CHARACTERISTICS (VDD = 5.0V unless noted) Input Frequency 10 12.5 or 25 27 MHz Output Clock Rise Time 0.8 to 2.0V 1.5 ns Output Clock Fall Time 2.0 to 0.8V 1.5 ns Output Clock Duty Cycle At VDD/2 40 50 60 % Frequency error All clocks 0 ppm Absolute Jitter, short term Variation from mean 150 ps Electrical Specifications Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability. External Components The ICS650-07C requires a minimum number of external components for proper operation. Decoupling capacitors of 0.01µF should be connected between each VDD and GND (pins 4 and 6, pins 16 and 14), as close to the ICS650-07 as possible. A series termination resistor of 33 Ω may be used for each clock output. The crystal must be connected as close to the chip as possible. The crystal should be a fundamental mode (do not use third overtone), parallel resonant. Crystal capacitors should be connected from pins X1 to ground and X2 to ground to optimize the initial accuracy. The value of these capacitors is given by the following equation, where CL is the crystal load capacitance: Crystal caps (pF) = (CL-6) x 2. So for a crystal with 16 pF load capacitance, two 20 pF caps should be used. |
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