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ICS627-01 Datasheet(PDF) 3 Page - Integrated Circuit Systems

Part # ICS627-01
Description  HDTV Set-Top Clock Source
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Manufacturer  ICST [Integrated Circuit Systems]
Direct Link  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS627-01 Datasheet(HTML) 3 Page - Integrated Circuit Systems

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ICS627-01
HDTV Set-Top Clock Source
MDS 627-01 B
3
Revision 051600
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126•(408) 295-9800tel • www.icst.com
PRELIMINARY INFORMATION
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS (n
note 1)
Supply voltage, VDD
Referenced to GND
7
V
Inputs and Clock Outputs
Referenced to GND
-0.5
VDD+0.5
V
Ambient Operating Temperature
0
70
°C
Soldering Temperature
Max of 10 seconds
260
°C
Storage temperature
-65
150
°C
DC CHARACTERISTICS (VDD = 3.3V
V unless noted)
Operating Voltage, VDD
3.15
3.30
3.45
V
Input High Voltage, VIH
2
V
Input Low Voltage, VIL
0.8
V
Input High Voltage, VIH, ICLK and CLKIN
(VDD/2)+1
VDD/2
V
Input Low Voltage, VIL, ICLK and CLKIN
VDD/2
(VDD/2)-1
V
Output High Voltage, VOH
IOH=-12mA
2.4
V
Output Low Voltage, VOL
IOL=12mA
0.4
V
Output High Voltage, VOH, CMOS level
IOH=-8mA
VDD-0.4
V
Operating Supply Current, IDD
No Load, note 2
TBD
mA
Short Circuit Current
Each output
±50
mA
Input Capacitance
7
pF
Frequency synthesis error
All clocks
0
ppm
AC CHARACTERISTICS (VDD = 3.3V
V unless noted)
Input Frequency
27.0
MHz
Output Clock Rise Time
0.8 to 2.0V
1.5
ns
Output Clock Fall Time
2.0 to 0.8V
1.5
ns
Output Clock Duty Cycle
At VDD/2
40
60
%
Maximum Absolute Jitter, short term
TBD
ps
Electrical Specifications
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. With all clocks at highest MHz.
The ICS627-01 requires a minimum number of external components for proper operation. Use a low
inductance ground plane, connect all GNDs to this. Connect 0.01µF decoupling caps across pins 5 and 10, 8
and 10, and 22 and 20, as close to the ICS627-01 as possible. A series termination resistor of 33
Ω may be
used for each clock output. The 27.000 MHz crystal must be connected as close to the chip as possible. The
crystal should be a fundamental mode, parallel resonant. Crystal capacitors should be connected from pins X1
to ground and X2 to ground. The value of these capacitors is given by the following equation, where CL is the
crystal load capacitance: Crystal caps (pF) = (CL-6) x 2. So for a crystal with 16pF load capacitance, two 20pF
caps should be used. If a clock input is used, drive it into X1 and leave X2 unconnected.
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