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74LVC3G07 Datasheet(PDF) 4 Page - NXP Semiconductors |
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74LVC3G07 Datasheet(HTML) 4 Page - NXP Semiconductors |
4 / 21 page 74LVC3G07 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 11 — 9 April 2013 4 of 21 NXP Semiconductors 74LVC3G07 Triple buffer with open-drain output 6.2 Pin description 7. Functional description [1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state. Fig 6. Pin configuration SOT996-2 Fig 7. Pin configuration SOT902-2 001aai252 74LVC3G07 Transparent top view 8 7 6 5 1 2 3 4 1A 3Y 2A GND VCC 1Y 3A 2Y 001aag243 3Y 3A 1A 2A 1Y 2Y Transparent top view 3 6 1 5 7 2 terminal 1 index area 74LVC3G07 Table 3. Pin description Symbol Pin Description SOT505-2, SOT765-1, SOT833-1, SOT1089, SOT996-2, SOT1116 and SOT1203 SOT902-2 1A, 2A, 3A 1, 3, 6 7, 5, 2 data input GND 4 4 ground (0 V) 1Y, 2Y, 3Y 7, 5, 2 1, 3, 6 data output VCC 8 8 supply voltage Table 4. Function table[1] Input nA Output nY LL HZ |
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