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ICS1892Y-10 Datasheet(PDF) 7 Page - Integrated Circuit Systems |
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ICS1892Y-10 Datasheet(HTML) 7 Page - Integrated Circuit Systems |
7 / 148 page Table of Contents ICS1892, Rev. D, 2/26/01 February 26, 2001 7 ICS1892 © 2000-2001, Integrated Circuit Systems, Inc. All rights reserved. Table of Contents Section Title Page 8.14 Register 19: Extended Control Register 2 ................................................. 98 8.14.1 Node/Repeater Configuration (bit 19.15) ................................................... 99 8.14.2 Hardware/Software Priority Status (bit 19.14) ........................................... 99 8.14.3 Remote Fault (bit 19.13) ............................................................................ 99 8.14.4 ICS Reserved (bits 19.12:2) ...................................................................... 99 8.14.5 Automatic 10Base-T Power-Down (bit 19.1) ........................................... 100 8.14.6 Automatic 100Base-TX Power-Down (bit 19.0) ....................................... 100 Chapter 9 ICS 1892 Pin Listing and Pin Descriptions ..................................... 101 9.1 ICS 1892 Pin Listings .............................................................................. 101 9.1.1 Pin Listing by Pin Number ....................................................................... 102 9.1.2 Pin Listings by Alphabetical Pin Name .................................................... 103 9.2 ICS 1892 Pin Descriptions ....................................................................... 104 9.2.1 Transformer Interface Pins ...................................................................... 104 9.2.2 Multifunction (Multiplexed) Pins: PHY Address and LED Pins ................ 105 9.2.3 Configuration Pins ................................................................................... 106 9.2.4 MAC/Repeater Interface Pins .................................................................. 109 9.2.5 Reserved Pins ......................................................................................... 118 9.2.6 Ground and Power Pins .......................................................................... 118 Chapter 10 DC and AC Operating Conditions .................................................. 120 10.1 Absolute Maximum Ratings ..................................................................... 120 10.2 Recommended Operating Conditions ..................................................... 120 10.3 Recommended Component Values ......................................................... 121 10.4 DC Operating Characteristics .................................................................. 122 10.4.1 DC Operating Characteristics for Supply Current .................................... 122 10.4.2 DC Operating Characteristics for TTL Inputs and Outputs ...................... 122 10.4.3 DC Operating Characteristics for REF_IN ............................................... 122 10.4.4 DC Operating Characteristics for Media Independent Interface .............. 123 10.5 Timing Diagrams ..................................................................................... 124 10.5.1 Timing for Clock Reference In (REF_IN) Pin ........................................... 124 10.5.2 Timing for Transmit Clock (TXCLK) Pin .................................................. 125 10.5.3 Timing for Receive Clock (RXCLK) Pin ................................................... 126 10.5.4 100M MII / 100M Stream Interface: Synchronous Transmit Timing ........ 127 10.5.5 10M MII: Synchronous Transmit Timing .................................................. 128 10.5.6 MII / 100M Stream Interface: Synchronous Receive Timing ................... 129 10.5.7 MII Management Interface Timing ........................................................... 130 10.5.8 10M Serial Interface: Receive Latency .................................................... 131 10.5.9 10M Media Independent Interface: Receive Latency .............................. 132 10.5.10 10M Serial Interface: Transmit Latency ................................................... 133 10.5.11 10M Media Independent Interface: Transmit Latency ............................. 134 10.5.12 MII / 100M Stream Interface: Transmit Latency ...................................... 135 10.5.13 MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission) ............ 136 |
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