HY51V(S)18163HG/HGL

Rev.0.1/Apr.01

4

Truth Table

Notes :

1. H : High ( inactive) L : Low ( active)

D : H or L

Early write cycle

twcs < 0ns

Delayed write cycle

3. Mode is determined by the OR function of the /UCAS and /LCAS (mode is set by earliest of /UCAS and /LCAS

active edge and reset by the latest of /UCAS and /LCAS inactive edge), However write operation and output

High-Z control are done independently by each /UCAS, /LCAS

ex) if /RAS = H to L, /UCAS = H, /LCAS = L, then /CAS-before-/RAS refresh cycle is selected

/RAS

/LCAS

/UCAS

/WE

/OE

Output

Operation

Notes

H

D

D

D

D

Open

Standby

1 ,3

L

L

H

H

L

Valid

Lower byte

Read cycle

1, 3

L

H

L

H

L

Valid

Upper byte

L

L

L

H

L

Valid

Word

L

L

H

L

D

Open

Lower byte

Early write cycle

1, 2, 3

L

H

L

L

D

Open

Upper byte

L

L

L

L

D

Open

Word

L

L

H

L

H

Undefined

Lower byte

Delayed write cycle

1, 2, 3

L

H

L

L

H

Undefined

Upper byte

L

L

L

L

H

Undefined

Word

L

L

H

H to L

L to H

Valid

Lower byte

Read-modify-write

Cycle

1, 3

L

H

L

H to L

L to H

Valid

Upper byte

L

L

L

H to L

L to H

Valid

Word

H to L

H

L

D

D

Open

Word

CBR refresh

or

Self refresh

(L-series)

1, 3

H to L

L

H

D

D

Open

Word

H to L

L

L

D

D

Open

Word

L

H

H

D

D

Open

Word

/RAS only refresh

cycle

1, 3

L

L

L

H

H

Open

Read cycle

(Output disabled)

1, 3