HV7121B

Electronics Industries Co., Ltd.

CMOS IMAGE SENSOR

System IC Division

With 8-bit ADC

This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any

responsibility for use of circuits described. NO patent licenses are implied.

DA41990615R_1.0

25

1999 Hyundai System IC

Division

(2) Frame Timing Diagram for Integration Time > (EffectiveWindowHeight * Scale)

Frame timing related registers are programmed to suit for the above condition as follows

RowStartAddress

= 6;

WindowHeight = 302;

ColumnStartAddress = 6;

WindowWidth = 402;

IntegrationTime = 600 [Line Mode];

EffectiveWindowHeight is “302” for (SensorArrayHeight > (RowStartAddress + WindowHeight + 1)), i.e. 314 > (6

+ 302 + 1), is met, and Scale is “ 1” for integration time is line mode. Therefore, (Integration Time <

EffectiveWindowHeight * Scale), i.e. 600 > 302 * 1, is met, and Idle Slot of Line Mode, i.e. (600 - 302) * 1024

clocks idle slot, is inserted before the next frame initiation.

Overall Frames Sequence

MCLK

ENB

VSYNC

Delay

Slots

Fig. 5 Initial Data Setup Time after ENB gets active

ENB

Deglitch

2 clocks

Sensor Reset

SensorArrayHeight clocks

[314 clocks]

One Line Time Delay

(SensorArrayWidth +

HBLANK) clocks

[417 clocks]

VSYNC

3 clocks

Integration Time * Scale

clocks

[600 * 414 clocks]

....

....

....