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HMS87C1302A Datasheet(PDF) 59 Page - Hynix Semiconductor |
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HMS87C1302A Datasheet(HTML) 59 Page - Hynix Semiconductor |
59 / 70 page HYUNDAI MicroElectronics HMS87C1304A/HMS87C1302A Jan. 2001 Preliminary 59 17.3 Internal RC-Oscillated Watchdog Timer Mode In the Internal RC-Oscillated Watchdog Timer mode, the on-chip oscillator is stopped. But internal RC oscillation circuit is oscillated in this mode. The on-chip RAM and Control registers are held. The port pins out the values held by their respective port data register, port direction regis- ters. The Internal RC-Oscillated Watchdog Timer mode is activated by execution of STOP instruction after set- ting the bit WAKEUP and RCWDT of CKCTLR to “01”. (This register should be written by byte opera- tion. If this register is set by bit manipulation instruc- tion, for example “set1” or “clr1” instruction, it may be undesired operation) Note: After STOP instruction, at least two or more NOP in- struction should be written Ex) LDM WDTR,#1111_1111B LDM CKCTLR,#0010_1110B LDM IRQH,#0 LDM IRQL,#0 STOP NOP NOP Release the Internal RC-Oscillated Watchdog Timer mode The exit from Internal RC-Oscillated Watchdog Timer mode is hardware reset or external interrupt. Reset re-de- fines all the Control registers but does not change the on- chip RAM. External interrupts allow both on-chip RAM and Control registers to retain their values. If I-flag = 1, the normal interrupt response takes place. In this case, if the bit WDTON of CKCTLR is set to “0” and the bit WDTE of IENH is set to “1”, the device will exe- cute the watchdog timer interrupt service routine.() How- ever, if the bit WDTON of CKCTLR is set to “1”, the device will generate the internal RESET signal and exe- cute the reset processing. () If I-flag = 0, the chip will resume execution starting with the instruction following the STOP instruction. It will not vector to interrupt service routine (refer to ). When exit from Internal RC-Oscillated Watchdog Timer mode by external interrupt, the oscillation stabilization time is required for normal operation. shows the timing di- agram. When release the Internal RC-Oscillated Watchdog Timer mode, the basic interval timer is activated on wake- up. It is increased from 00H until FFH. The count overflow is set to start normal operation. Therefore, before STOP in- struction, user must be set its relevant prescaler divide ratio to have long enough time (more than 20msec). This guar- antees that oscillator has started and stabilized. By reset, exit from internal RC-Oscillated Watchdog Tim- er mode is shown in . Figure 17-5 Internal RCWDT Mode Releasing by External Interrupt or WDT Interrupt RCWDT Mode Normal Operation Oscillator (XIN pin) N+1 NN+2 00 01 FE FF 00 00 N-1 N-2 Clear Basic Interval Timer STOP Instruction Execution Normal Operation Stabilization Time tST > 20mS Internal Clock External Interrupt BIT Counter Internal RC Clock (or WDT Interrupt) Preliminary |
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