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S1L35000 Datasheet(PDF) 11 Page - Epson Company |
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S1L35000 Datasheet(HTML) 11 Page - Epson Company |
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11 / 106 page  Chapter 1: Overview 6 EPSON GATE ARRAY S1L35000 SERIES DESIGN GUIDE 1.4 Overview of Gate Array Development Flow Gate arrays are developed jointly by the customer and EPSON. System design, circuit design, and test pattern design is performed by the customer, based on various reference materials, including the cell libraries provided to the customer by EPSON. Various modes of interface, listed below, are possible between the customer and EPSON during design, depending on the stage in gate array development wherein the customer interfaces with EPSON. When interfacing with EPSON, the customer is to provide the necessary data and documents to EPSON. The customer performs schematic capture, logic synthesis and simulation using EDA software and Auklet* supported by EPSON. Place and route is performed by EPSON. Both the customer and EPSON are responsible for final sign-off simulations. Note) * : Auklet is the EPSON's ASIC desgin support system that can run on a personal computer- OS : MS-Windows 95/98, NT platform. The simulation is currently supported by the following EDA software: • Verilog-XL (*1) • VSS (*2) • ModelSim (*3) Note) *1 : Verilog-XL is a registered trademark of Cadence Desgin Systems Corporation, USA. *2 : VSS is a registered trademark of Synopsys Inc., USA. *3 : ModelSim is a registered trademark of Model Technology Corp., USA. For more information, refer to the Gate Array Technical Guide or contact to our sales office for technical support. |
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