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HMS81C4X60 Datasheet(PDF) 97 Page - Hynix Semiconductor |
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HMS81C4X60 Datasheet(HTML) 97 Page - Hynix Semiconductor |
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97 / 110 page  HMS81C4x60 November 2001 Ver 1.1 95 22. RESET The HMS81C4x60 have two types of reset generation pro- cedures; one is an external reset input, other is a watch-dog timer reset. Table 22-1 shows on-chip hardware initializa- tion by reset action. Table 22-1 Initializing Internal Status by Reset Action 22.1 External Reset Input The reset input is the RESET pin, which is the input to a Schmitt Trigger. A reset in accomplished by holding the RESET pin low for at least 8 oscillator periods, within the operating voltage range and oscillation stable, a reset is ap- plied and the internal state is initialized. After reset, 64ms (at 4 MHz) add with 7 oscillator periods are required to start execution as shown in Figure 22-2 . Internal RAM is not affected by reset. When VDD is turned on, the RAM content is indeterminate. Therefore, this RAM should be initialized before reading or testing it. When the RESET pin input goes high, the reset operation is released and the program execution starts at the vector address stored at addresses FFFEH - FFFFH. A connecting for simple power-on-reset is shown in Figure 22-1 . Figure 22-1 Simple Power-on-Reset Circuit Figure 22-2 Timing Diagram after RESET On-chip Hardware Initial Value On-chip Hardware Initial Value Program counter PC (FFFFH) - (FFFEH) Peripheral clock Off RAM page register DPGR 00H Watchdog timer Disable G-flag of PSW G 0 Control registers Refer to Table 8-1 on page 22 RESET + − VDD GND MCU MAIN PROGRAM Oscillator (XIN pin) ? ? FFFE FFFF Stabilization Time tST = 62.5mS at 4.19MHz RESET ADDRESS DATA 1 2 3 4 5 6 7 ?? Start ? ? ? FE ? ADL ADH OP BUS BUS RESET Process Step tST = x 256 fMAIN ÷1024 1 Fetch |
Similar Part No. - HMS81C4X60 |
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Similar Description - HMS81C4X60 |
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