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HMS81C43XX Datasheet(PDF) 63 Page - Hynix Semiconductor |
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HMS81C43XX Datasheet(HTML) 63 Page - Hynix Semiconductor |
63 / 100 page HMS81C43xx / GMS87C4060 63 November 2001 ver 1.2 18. I2C Bus Interface The I2C Bus interface circuit is shown in Figure 18-1 . The multi-master I2C Bus interface is a serial communica- tions circuit, conforming to the Phlips I2C Bus data trans- fer format. This interface, offering both arbitration lost detection and a synchronous functions, is useful for the multi-master serial communications. This multi-master I2C Bus interface circuit consists of the I2C address register, the I2C data shift register, the I2C clock control register, the I2C control register, the I2C sta- tus register and other control circuits. The more details about registers are shown Figure 18-2 ~ Figure 18-6 . Figure 18-1 Block Diagram of multi-master I2C circuit Control The HMS81C43xx/GMS87C4060 contains two I2C Bus interface modules. It supports multi-master function, so it contains arbitration lost detection, synchronization func- tion,etc. I2C address register It contains slave address (7bit) which is used during slave mode and Read/Write bit. Bit 7 ~ 0 : Slave address 6~0 Note: Bit 7~0 (SAD6~0) store slave address. The address data transmitted from the master is compared with the con- tents of these bits. ICAR [D8H] IFI2CR Bit counter SCL Address comparator ICDR [D9H] D7 D6 D5 D4 D3 D2 D1 D0 Interrupt Generation Circuit Data Control Circuit ICSR [00DAH] MST TRX BB PIN AL AAS AD0 LRB Noise Elimination Circuit AL Circuit BB Circuit Clock Control Circuit Noise Elimination Circuit ICCR1 [00DBH] BSE L 1 ~ 0 ALS ESO BC 2 ~ 0 ICCR2 [DCH] ACLK ACK 1 C CR3 ~ 0 Clock division External clock SDA SAD6 SDA5 SDA4 SDA3 SDA2 SDA1 SDA0 R/W ITEM Function Format Philips I2C standard 7bit addressing format Communication mode Master transmitter Master receiver Slave transmitter Slave receiver SCL clock frequency 66.6KHz ~ 500KHz (fex=12MHz) 44.4KHz ~ 333.3KHz (fex=8MHz) ITEM Function |
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