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HMS81004E Datasheet(PDF) 27 Page - Hynix Semiconductor |
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HMS81004E Datasheet(HTML) 27 Page - Hynix Semiconductor |
27 / 77 page HMS81004E/08E/16E/24E/32E 24 JUNE 2001 Ver 1.00 00DFh PORT R2 OPEN DRAIN ASSIGN REG. R2ODC R/W 00000000b 00E0h Reserved 00E1h Reserved 00E2h Reserved 00E3h Reserved 00E4h PORT R0 OPEN DRAIN ASSIGN REG. R0ODC R/W 00000000b 00E5h Reserved 00E6h Reserved 00E7h Reserved 00E8h Reserved 00E9h Reserved 00EAh Reserved 00EBh Reserved 00ECh Reserved 00EDh Reserved 00EEh Reserved 00EFh Reserved 00F0h SLEEP MODE REG. SLPM W - - - - - - - 0b 00F1h Reserved 00F2 Reserved 00F3h Reserved 00F4h Reserved 00F5h Reserved 00F6h STANDBY RELEASE LEVEL CONT. REG. 0 SRLC0 W 00000000b 00F7h STANDBY RELEASE LEVEL CONT. REG. 1 SRLC1 W 00000000b 00F8h PORT R0 PULL-UP REG. CONT. REG. R0PC W 00000000b 00F9h PORT R1 PULL-UP REG. CONT. REG. R1PC W 00000000b 00FAh PORT R2 PULL-UP REG. CONT. REG. R2PC W 00000000b 00FBh Reserved 00FCh Reserved 00FDh Reserved 00FEh Reserved 00FFh Reserved Registers are controlled by byte manipulation instruction such as LDM etc., do not use bit manipulation W Registers are controlled by both bit and byte manipulation instruction. R/W instruction such as SET1, CLR1 etc. If bit manipulation instruction is used on these registers, content of other seven bits are may varied to unwanted value. - : this bit location is reserved. |
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