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GM71V17403C Datasheet(PDF) 4 Page - Hynix Semiconductor

Part No. GM71V17403C
Description  4,194,304 WORDS x 4 BIT CMOS DYNAMIC RAM
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Maker  HYNIX [Hynix Semiconductor]
Homepage  http://www.skhynix.com/ko/index.jsp
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GM71V17403C Datasheet(HTML) 4 Page - Hynix Semiconductor

 
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GM71V17403C
GM71VS17403CL
Rev 0.1 / Apr’01
Capacitance (VCC = 3.3V +/- 0.3V, TA = 25C)
AC Characteristics (VCC = 3.3V +/- 0.3V, VSS = 0V, TA = 0 ~ 70C, Notes 1, 2, 18)
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)
Symbol
Parameter
Note
CI1
CI2
CI/O
Input Capacitance (Address)
Input Capacitance (Clocks)
Output Capacitance (Data-In/Out)
1
1
1, 2
Unit
pF
pF
pF
Max
5
7
7
Min
-
-
-
Test Conditions
Input rise and fall times : 2ns
Input levels : VIL = 0V, VIH = 3V
Input timing reference levels : 0.8V, 2.0V
Output timing reference levels : 0.8V, 2.0V
Output load : 1 TTL gate + CL (100pF)
(Including scope and jig)
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. CAS = VIH to disable DOUT.
Symbol
Parameter
Note
Max
Unit
Min
Max
Min
Max
Min
tRC
Random Read or Write Cycle Time
84
-
104
-
124
-
tRP
RAS Precharge Time
30
-
40
-
50
-
tRAS
RAS Pulse Width
50 10,000
60 10,000
70 10,000
tCAS
CAS Pulse Width
8 10,000
10,000
10,000
10
13
tASR
Row Address Set up Time
0
-
-
-
0
0
tRAH
Row Address Hold Time
8
-
-
-
10
10
tASC
Column Address Set-up Time
0
-
-
-
0
0
tCAH
Column Address Hold Time
8
-
-
-
10
13
tRCD
RAS to CAS Delay Time
12
37
45
52
14
14
3
tRAD
RAS to Column Address Delay Time
10
25
30
35
12
12
4
tRSH
RAS Hold Time
10
-
-
-
13
13
tCSH
CAS Hold Time
35
-
-
-
40
45
tCRP
CAS to RAS Precharge Time
5
-
-
-
5
5
tT
Transition Time (Rise and Fall)
2
50
50
50
2
2
7
tDZO
OE Delay Time from DIN
0
-
-
-
0
0
tDZC
CAS Delay Time from DIN
0
-
-
-
0
0
GM71V(S)17403
C/CL-5
OE to DIN Delay Time
13
-
-
-
15
18
5
6
6
tCP
CAS Precharge Time
8
-
10
-
13
-
tODD
GM71V(S)17403
C/CL-6
GM71V(S)17403
C/CL-7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns


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