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GM71C17800C Datasheet(PDF) 8 Page - Hynix Semiconductor

Part # GM71C17800C
Description  2,097,152 WORDS x 8 BIT CMOS DYNAMIC RAM
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

GM71C17800C Datasheet(HTML) 8 Page - Hynix Semiconductor

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GM71C17800C
GM71CS17800CL
Rev 0.1 / Apr’01
AC Measurements assume tT = 5ns.
An initial pause of 200
is required after power up followed by a minimum of eight
initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-
RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS
refresh cycles are required.
Operation with the tRCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a
reference point only; if tRCD is greater than the specified tRCD(max) limit, then access time is
controlled exclusively by tCAC.
Operation with the tRAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a
reference point only; if tRAD is greater than the specified tRAD(max) limit, then access time is
controlled exclusively by tAA.
Either tODD or tCDD must be satisfied.
Either tDZO or tDZC must be satisfied.
VIH (min) and VIL (max) are reference levels for measuring timing of input signals.
Also,
transition times are measured between VIH (min) and VIL (max).
Assumes that tRCD <= tRCD (max) and tRAD <= tRAD (max).
If tRCD or tRAD is greater than the
maximum recommended value shown in this table, tRAC exceeds the value shown.
Measured with a load circuit equivalent to 2TTL loads and 100pF.(VOH =2.4V , VOL= 0.4V)
Assumes that tRCD >= tRCD (max) and tRAD <= tRAD (max).
Assumes that tRCD <= tRCD (max) and tRAD >= tRAD (max).
Either tRCH or tRRH must be satisfied for a read cycles.
tOFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition
and are not referred to output voltage levels.
tWCS, tRWD, tCWD and tAWD and tCPW are not restrictive operating parameters. They are included in
the data sheet as electrical characteristics only; if tWCS >=tWCS(min), the cycle is an early write
cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle;
if tRWD>=tRWD(min), tCWD>=tCWD(min), and tAWD>=tAWD(min) or tCWD>=tCWD(min),
tAWD>=tAWD(min), and tCPW>=tCPW(min), the cycle is a read -modify- write and the data output
will contain data read from the selected cell; if neither of the above sets of conditions is
satisfied, the condition of the data out (at access time) is indeterminate.
These parameters are referred to CAS leading edge in early write cycle and to WE leading edge
in a delayed write or a read modify write cycle.
tRASP defines RAS pulse width in fast page mode cycles.
Access time is determined by the longer of tAA or tCAC or tACP.
In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying
data to the device. After RAS is reset, if tOEH>=tCWL, the I/O pin will remain open circuit (high
impedance): if tOEH<=tCWL, invalid data will be out at each I/O.
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