Electronic Components Datasheet Search |
|
AT40KEL040 Datasheet(PDF) 2 Page - ATMEL Corporation |
|
AT40KEL040 Datasheet(HTML) 2 Page - ATMEL Corporation |
2 / 42 page 2 AT40KEL040 4155I–AERO–06/06 *** Description The AT40KEL040 is a fully PCI-compliant, SRAM-based FPGA with distributed 18 ns programmable synchronous/asynchronous, dual port/single port SRAM, 8 global clocks, Cache Logic ability (partially or fully reconfigurable without loss of data), automatic com- ponent generators, and 46,000 ASIC gates. I/O counts range from 129 to 384 in Aero- space standard packages and support 3.3V. The AT40KFL040 is a 5V tolerant version. The AT40KEL040 is designed to quickly implement high performance, large gate count designs through the use of synthesis and schematic-based tools used Windows® / Linux® platform. Atmel’s design tools provide easy integration with industry standard tools such as Synplicity, Modelsim and Leonardo Spectrum/Precision Synthesis. See the IDS datasheet for other supported tools. The AT40KEL040 can be used as a co-processor for high-speed (DSP/processor- based) designs by implementing a variety of compute-intensive, arithmetic functions. These include adaptive finite impulse response (FIR) filters, Fast Fourier Transforms (FFT), convolvers, interpolators and discrete-cosine transforms (DCT) that are required for video compression and decompression, encryption, convolution and other multime- dia applications. Fast, Flexible and Efficient SRAM The AT40KEL040 FPGA offers a patented distributed 18 ns SRAM capability where the RAM can be used without losing logic resources. Multiple independent, synchronous or asynchronous, dual port or single port RAM functions (FIFO, scratch pad, etc.) can be created using Atmel’s macro generator tool. Fast, Efficient Array and Vector Multipliers The AT40KEL040’s patented 8-sided core cell with direct horizontal, vertical and diago- nal cell-to-cell connections implements ultra fast array multipliers without using any bus- ing resources. The AT40KEL040’s Cache Logic capability enables a large number of design coefficients and variables to be implemented in a very small amount of silicon, enabling vast improvement in system speed at much lower cost than conventional FPGAs. Cache Logic Design The AT40KEL040 is capable of implementing Cache Logic (Dynamic full/partial logic reconfiguration, without loss of data, on-the-fly) for building adaptive logic and systems. As new logic functions are required, they can be loaded into the logic cache without los- ing the data already there or disrupting the operation of the rest of the chip; replacing or complementing the active logic. The AT40KEL040 can act as a reconfigurable co-pro- cessor. Automatic Component Generators The AT40KEL040 FPGA family is capable of implementing user-defined, automatically generated, macros in multiple designs; speed and functionality are unaffected by the macro orientation or density of the target device. This enables the fastest, most predict- able and efficient FPGA design approach and minimizes design risk by reusing already Table 1. AT40KEL040 Device AT40KEL040 Available ASIC Gates (50% typ. routable) 46K Rows x Columns 48 x 48 Core Cells 2,304 Registers 3,056 RAM Bits 18,432 I/O (max) 384 |
Similar Part No. - AT40KEL040_14 |
|
Similar Description - AT40KEL040_14 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |