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WINC1000-MR110PA Datasheet(PDF) 14 Page - ATMEL Corporation |
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WINC1000-MR110PA Datasheet(HTML) 14 Page - ATMEL Corporation |
14 / 25 page 14 Atmel ATWILC1000-MR110PA [PRELIMINARY DATASHEET] Atmel-42380B-SmartConnect-WILC1000-MR110PA_Datasheet_10/2014 9.2 UART When the module is configured for SPI mode by connecting the SDIO~_SPI_CFG pin to VDDIO, the ATWILC1000-MR110PA has a Universal Asynchronous Receiver / Transmitter (UART) interface available on pins J14 and J19. It can be used for control or data transfer if the baud rate is sufficient for a given application. The UART is compatible with the RS-232 standard, where NMC1000 operates as Data Terminal Equipment (DTE). It has a two-pin RXD/TXD interface. The UART features programmable baud rate generation with fractional clock division, which allows transmission and reception at a wide variety of standard and non-standard baud rates. The UART input clock is selectable between 10MHz, 5MHz, 2.5MHz, and 1.25MHz. The clock divider value is programmable as 13 integer bits and 3 fractional bits (with 8.0 being the smallest recommended value for normal operation). This results in the maximum supported baud rate of 10MHz / 8.0 = 1.25 MBd. The UART can be configured for seven or eight bit operation, with or without parity, with four different parity types (odd, even, mark, or space), and with one or two stop bits. It also has Rx and Tx FIFOs, which ensure reliable high speed reception and low software overhead transmission. FIFO size is 4 x 8 for both Rx and Tx direction. The UART also has status registers showing the number of received characters available in the FIFO and various error conditions, as well the ability to generate interrupts based on these status bits. An example of UART receiving or transmitting a single packet is shown in Figure 9-2. This example shows 7-bit data (0x45), odd parity, and two stop bits. See the ATWILC1000-MR110PA Programming Guide for information on configuring the UART. Figure 9-2. Example of UART Rx or Tx Packet 9.3 SDIO Interface When the module is configured for SDIO mode by connecting the SDIO~_SPI_CFG pin to Ground, the ATWILC1000-MR110PA has a SDIO interface. The SDIO interface can be used for control and for serial I/O of 802.11 data. The SDIO pins are mapped as shown in Figure 9-3. The SDIO interface is available immediately following reset when pin 10 (SPI_CFG) is tied to ground. The ATWILC1000-MR110PA SDIO is a full speed interface. The interface supports the 1-bit/4-bit SD transfer mode at the clock range of 0-50MHz. The Host can use this interface to read and write from any register within the chip as well as configure the ATWILC1000-MR110PA for data DMA. |
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