AT89LP4052_14 datasheet(75/94 Pages) ATMEL

Part #	AT89LP4052

Description	Single Clock Cycle per Byte Fetch

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Manufacturer	ATMEL [ATMEL Corporation]

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75

3547J–MICRO–10/09

AT89LP2052/LP4052

23.5.2

Power-down Sequence

Execute this sequence to power-down the device after serial programming.

1.

Tri-state MOSI (P1.5).

2.

Bring SCK (P1.7) to “L”.

3.

Bring RST to “L”.

4.

Bring SS (P1.4) to “L”

5.

Power off Vcc.

Figure 23-23. Serial Programming Power-down Sequence

Note:

The waveforms on this page are not to scale.

23.5.3

ISP Start Sequence

Execute this sequence to enter ISP when the device is already operational.

1.

Bring SS (P1.4) to “H”.

2.

Tri-state MISO (P1.6).

3.

Bring RST to “H”.

4.

Bring SCK (P1.7) to “L”.

Figure 23-24. In-System Programming (ISP) Start Sequence

VCC

RST

SS

SCK

HIGH Z

MISO

HIGH Z

MOSI

VCC

RST

SS

SCK

HIGH Z

MOSI

HIGH Z

MISO

XTAL1

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