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ATMEGA169V Datasheet(PDF) 34 Page - ATMEL Corporation |
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ATMEGA169V Datasheet(HTML) 34 Page - ATMEL Corporation |
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34 / 365 page  34 ATmega169/V 2514P–AVR–07/06 The LCD controller and Timer/Counter2 can be clocked both synchronously and asyn- chronously in Power-save mode. The clock source for the two modules can be selected independent of each other. If neither the LCD controller nor the Timer/Counter2 is using the asynchronous clock, the Timer/Counter Oscillator is stopped during sleep. If neither the LCD controller nor the Timer/Counter2 is using the synchronous clock, the clock source is stopped during sleep. Note that even if the synchronous clock is running in Power-save, this clock is only available for the LCD controller and Timer/Counter2. Standby Mode When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down with the exception that the Oscillator is kept running. From Standby mode, the device wakes up in six clock cycles. Notes: 1. Only recommended with external crystal or resonator selected as clock source. 2. If either LCD controller or Timer/Counter2 is running in asynchronous mode. 3. For INT0, only level interrupt. Power Reduction Register The Power Reduction Register, PRR, provides a method to stop the clock to individual peripherals to reduce power consumption. The current state of the peripheral is frozen and the I/O registers can not be read or written. Resources used by the peripheral when stopping the clock will remain occupied, hence the peripheral should in most cases be disabled before stopping the clock. Waking up a module, which is done by clearing the bit in PRR, puts the module in the same state as before shutdown. Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall power consumption. See “Supply Current of I/O modules” on page 310 for exam- ples. In all other sleep modes, the clock is already stopped. Power Reduction Register - PRR • Bit 7..5 - Res: Reserved bits These bits are reserved in ATmega169 and will always read as zero. Table 15. Active Clock Domains and Wake-up Sources in the Different Sleep Modes. Active Clock Domains Oscillators Wake-up Sources Sleep Mode clk CPU clk FLASH clk IO clk ADC clk ASY Main Clock Source Enabled Timer Osc Enabled INT0 and Pin Chang e USI Start Condition LCD Controller Timer2 SPM/ EEPROM Ready ADC Other I/O Idle X X X X X(2) XX X X X X X ADC Noise Reduction X X X X(2) X(3) XX(2) X(2) XX Power-down X(3) X Power-save X X X(3) XX X Standby(1) XX(3) X Bit 765 4 3 2 1 0 – – – PRLCD PRTIM1 PRSPI PRUSART0 PRADC PRR Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 |
Similar Part No. - ATMEGA169V_14 |
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