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ATAR092-C Datasheet(PDF) 44 Page - ATMEL Corporation |
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ATAR092-C Datasheet(HTML) 44 Page - ATMEL Corporation |
44 / 108 page 44 4593D–4BMCU–05/06 ATAR092-C/ATAR892-C 5.3.2.7 Duty Cycle Generator The duty cycle generator generates duty cycles of 25%, 33% or 50%. The frequency at the duty cycle generator output depends on the duty cycle and the Timer 2 prescaler setting. The DCG-stage can also be used as additional programmable prescaler for Timer 2. Figure 5-23. DCG Output Signals Table 5-9. Timer 2 Duty Cycle Bits T2D1 T2D0 Function of Duty Cycle Generator (DCG) Additional Divider Effect 1 1 Bypassed (DCGO0) /1 1 0 Duty cycle 1/1 (DCGO1) /2 0 1 Duty cycle 1/2 (DCGO2) /3 0 0 Duty cycle 1/3 (DCG03) /4 T2MS1 Timer 2 Mode Select bit 1 T2MS0 Timer 2 Mode Select bit 0 Table 5-10. Timer 2 Mode Select Bits Mode T2MS1 T2MS0 Clock Output (POUT) Timer 2 Modes 1 1 1 4-bit counter overflow (OVF1) 12-bit compare counter, the DCG have to be bypassed in this mode 2 1 0 4-bit compare output (CM1) 8-bit compare counter with 4-bit programmable prescaler and duty cycle generator 3 0 1 4-bit compare output (CM1) 8-bit compare counter clocked by SYSCL or the external clock input T2I, 4-bit prescaler run, the counter 2/1 starts after writing mode 3 4 0 0 4-bit compare output (CM1) 8-bit compare counter clocked by SYSCL or the external clock input T2I, 4-bit prescaler stop and resets DCGIN DCGO0 DCGO1 DCGO2 DCGO3 |
Similar Part No. - ATAR092-C_14 |
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Similar Description - ATAR092-C_14 |
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