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AT91R40807 Datasheet(PDF) 29 Page - ATMEL Corporation |
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AT91R40807 Datasheet(HTML) 29 Page - ATMEL Corporation |
29 / 153 page 29 AT91X40 Series 1354D–ATARM–08/02 Figure 17. Data Hold Time In early read protocol the data can remain valid longer than in standard read protocol due to the additional wait cycle which follows a write access. Wait States The EBI can automatically insert wait states. The different types of wait states are listed below: • Standard wait states • Data float wait states • External wait states • Chip select change wait states • Early read wait states (see “Read Protocols” ) Standard Wait States Each chip select can be programmed to insert one or more wait states during an access on the corresponding device. This is done by setting the WSE field in the corresponding EBI_CSR. The number of cycles to insert is programmed in the NWS field in the same register. Below is the correspondence between the number of standard wait states programmed and the number of cycles during which the NWE pulse is held low: 0 wait states1/2 cycle 1 wait state1 cycle For each additional wait state programmed, an additional cycle is added. ADDR NWE Data Output MCK |
Similar Part No. - AT91R40807_14 |
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Similar Description - AT91R40807_14 |
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