7

ATA664151 [DATASHEET]

9268H–AUTO–08/14

3.14

VDIV Input/Output Pin

This pin handles two different functions. During the VCC startup and watchdog reset phase (pin NRES driven to LOW), the

pin acts as input and determines the setting of the “WDD” bit within the SPI configuration register (see Figure 3-2). In other

words, if the window watchdog operation shall be disabled directly after power-up (e.g., for microcontroller programming or

debugging purposes), pin VDIV must be tied to HIGH level until the reset phase ends (pin NRES has a positive slope from

LOW to HIGH). In other cases, such as when pin VDIV is not driven actively by the application, the signal is assessed as

LOW and the WDD bit (watchdog disable) is thus also low and the window watchdog is operational (see Figure 3-2).

Figure 3-2. WDD Configuration Bit Setup During VCC Startup

During normal operation this pin provides a low-voltage signal for the ADC such as for a microcontroller. It is sourced either

by the VBATT pin or one of the switch input pins CS1 to CS8. An external ceramic capacitor is recommended for low-pass

filtering of this signal. If selected in the configuration register of the SPI, this pin guarantees a voltage- and temperature-

stable output ratio of the selected test input and is available in all modes except sleep mode. Please note that the current

validity if the VDIV output pin is being used in this low-power mode. The voltage on this pin is actively clamped to VCC if the

input value would lead to higher values.

3.15

IREF Output Pin

This pin is the connection for an external resistor towards ground. It provides a regulated voltage which will cause a resistor-

dependent current used as reference for the current sources in the switch interface I/O ports. The resistor should be placed

closely to the pin without any additional capacitor. A fail-safe circuitry detects if the resistor is missing or if there is a short

towards ground or VCC on this pin. An internal fail-safe current is generated in this event. Please see also Section 8. “Switch

Interface Unit” on page 22 for further details.

3.16

CS1 to CS8 High-voltage Input/Output Pins

These pins are intended for contact monitoring and/or constant current sourcing. A total of eight I/Os (pins CS1 through

CS8) are available, of which three (CS1, CS2 and CS3) can be configured either as current sources (such as for switches

towards ground) or as current sinks (such as for switches towards battery). The other five pins (CS4 to CS8) have only

current sourcing capability. Apart from a high voltage (HV) comparator for simple switches, the I/Os are also equipped with a

voltage divider to enable analog voltage measurements on HV pins by using the ADC of the application’s microcontroller

(see Section 3.14 “VDIV Input/Output Pin” on page 7 for further details). Also, each input can trigger an interrupt upon state

change even during Active Low-power Mode. If one or more CSx pins are not needed, can be left open or directly connected

to VS.

Note:

Unused CSx-pins should be connected directly to VS.

3.17

PWM1..3 Input Pins

These pins can be used to control the switch interface current sources directly, such as for pulse width-modulated load

control or for pulsed switch scanning. They accept logic level signals from the microcontroller and are equipped with pull-

down structures so in case of an open connection, the input is well defined. For more information see Section 8. “Switch

Interface Unit” on page 22.

The assignment of the current sources to the three PWM input pins is described in Section 8.1 “Current Sources” on page

22.

NRES

VDIV (driven externally)

WDD config bit state

Logic Level “A”

Logic Level “A”

Z (high imp.)

X

“LOW” from VCC startup