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83052AGILFT Datasheet(PDF) 7 Page - Integrated Device Technology

Part No. 83052AGILFT
Description  2 1 single-ended multiplexer
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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83052AGILFT Datasheet(HTML) 7 Page - Integrated Device Technology

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ICS83052I REVISION B DECEMBER 8, 2011
7
©2011 Integrated Device Technology, Inc.
ICS83052I Data Sheet
2:1, SINGLE ENDED MULTIPLEXER
ADDITIVE PHASE JITTER
Additive Phase Jitter (Random)
at 155.52MHz (12kHz - 20MHz)
= 0.18ps (typical)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz
As with most timing specifications, phase noise measurements
has issues relating to the limitations of the equipment. Often
the noise floor of the equipment is higher than the noise floor of
band to the power in the fundamental. When the required offset
is specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
the device. This is illustrated above. The device meets the noise
floor of what is shown, but can actually be lower. The phase
noise is dependant on the input source and measurement
equipment.
OFFSET FROM CARRIER FREQUENCY (HZ)
1k
10k
100k
1M
10M
100M


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