406

Fiber Optic “Light to Logic”

Receiver with Clock Recovery

Preliminary Technical Data

RGR2622

Features

• Light to Logic 20-Pin DIP

Receiver Offers ECL

Compatibility

• Sensitivity:

–31 dBm

• Phase-Locked Loop (PLL)

Timing Recovery Circuit

• Meets All SONET Jitter

Requirements

(CCITT G.958)

• Single +5 V Supply,

Typically <1.00 W

• SONET/SDH Compliant

Applications

• Telecommunication

Networks

• SONET OC12 and SDH

STM4 Compatible

• Local and Metropolitan Area

Networks

• ATM Single Mode Public

Network

• Military Communications

and Control Systems

• Digital Cable TV Networks

Description

The RGR2622 receiver provides

optical signal conversion and

processing. It converts 1200 nm

to 1600 nm wavelength lightwave

information into an electrical

signal at data rates of 622 Mb/s.

Each receiver contains an InGaAs

PIN photodiode, a high sensitiv-

ity, wide dynamic range transim-

pedance amplifier, capacitively

coupled to a PLL based clock

recovery circuit. The clock and

data outputs are retimed

complementary PECL.

A complementary CMOS

compatible low light alarm is also

provided.

Preliminary Product Disclaimer

This preliminary data sheet is provided to assist you in the evaluation of engineering samples of the product which is under development.

Until Hewlett-Packard releases this product for general sales, HP reserves the right to alter prices, specifications, features, capabilities,

function, manufacturing release dates, and even general availability of the product at any time.

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