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ATA6286C Datasheet(PDF) 25 Page - ATMEL Corporation

Part # ATA6286C
Description  Embedded AVR Microcontroller with LF Receiver and UHF Transmitter
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

ATA6286C Datasheet(HTML) 25 Page - ATMEL Corporation

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ATA6286C [DATASHEET]
9308C–RFID–09/14
Bit 4 – CCS: Core Clock Select Bit
This bit selects from the FRC oscillator clock and all other clock sources. The CCS bit must be written to logic one to enable
the mode selected with the CMM[1..0] bits. If the CCS bit is written to logic zero, the FRC oscillator clock is enabled. When
the CCS bit is logic one, the CMM[1..0] bits in CMCR must not be changed. After external clock fail detection, the CCS bit is
written to zero.
Bit 3 – CMONEN: Clock Monitoring Enable
This bit controls clock monitoring. The CMONEN bit must be written to logic one to enable clock monitoring. If the CMONEN
bit is written to logic zero, clock monitoring is always disabled.
Bit 2 – SRCD: Slow RC oscillator (SRC) Disable Bit
This bit controls the SRC oscillator used as the clock source for the watchdog (also called WDRC). The SRCD bit must be
written to logic one to disable (stop) the SRC, and if the SRCD bit is written to logic zero, the SRC is always enabled
(running). The SRC oscillator cannot be disabled if the fuse bit WDRCON is programmed.
Bits 1..0 – CMM1..0: Clock Management Mode Bits 1 - 0
These bits select the input clock source (CL) of the system clock prescaler. Bits CMM1 and CMM0 are not affected by an
external clock fail. Before changing the CMM1..0 bits, CCS must first be cleared. After the CMM1..0 bits have been changed,
CCS can be set to logic one.
3.7.1.3 Clock Management Status Register – CMSR
Bits 7 to 1 – Res: Reserved Bits
These bits are reserved bits on the ATA6289 and are always read as zero.
Bit 0 – ECF: External Clock Input Flag Bit
This bit is set if the clock monitoring circuit detects a breakdown of the selected external input clock (ECIN0 or ECIN1). ECF
is automatically cleared when the clock monitoring interrupt vector is executed. Alternatively, ECF can be cleared by writing
a logic one to its bit location.
Table 3-4.
Core Clock Select Bit Description
CCS
Description
0
The FRC oscillator generates CL
1
The SRC oscillator or an External Clock source (ECL) generates depending on the setting of the
CMM[1..0] bits.
Table 3-5.
Clock Source of the System Clock Prescaler Select Bit Description
Mode
Clock Source for System Clock Prescaler (CL)
CMM1
CMM0
CCS = 0
CCS = 1
0
0
0
FRC
Reserved
1
0
1
FRC
Reserved
2
1
0
FRC
SRC
3
1
1
FRC
ECL
Bit
765
43210
-
-
-
-
-
-
-
ECF
CMSR
Read/Write
RRRR
RRR
R/W
Initial Value
000
00000


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