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LC79401KNE Datasheet(PDF) 6 Page - ON Semiconductor |
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LC79401KNE Datasheet(HTML) 6 Page - ON Semiconductor |
6 / 8 page LC79401KNE No. A1419-6/8 Pin Function Pin No Symbol I/O Function 90 VDD 88 VSS 85 VEE Supply VDD-VSS : Logic power supply VDD-VEE : LCD drive circuit power supply 82 V1 83 V3 84 V4 Supply LCD drive level power supply V1,VEE : Selected level V3,V4 : Unselected level 99 CP I Display data acquisition clock (falling edge trigger) 87 LOAD I Display data latch clock (falling edge trigger) The display data LCD drive signal is output on the falling edge. 95 96 97 98 DI4 DI3 DI2 DI1 I Display data LCD drive output LCD display H Selected level On L Unselected level Off 91 R/L I Control pin that inverts the data output destination Number of clock R/L Data input 1 2 3 • • • 18 19 20 DI1 O77 O73 O69 • • • O9 O5 O1 DI2 O78 O74 O70 • • • O10 O6 O2 DI3 O79 O75 O71 • • • O11 O7 O3 L DI4 O80 O76 O72 • • • O12 O8 O4 DI1 O4 O8 O12 • • • O72 O76 O80 DI2 O3 O7 O11 • • • O71 O75 O79 DI3 O2 O6 O10 • • • O70 O74 O78 H DI4 O1 O5 O9 • • • O69 O73 O77 86 M I LCD drive output alternation signal 81 CDI I Chip disable pin High level : Data is not acquired. Low level : Data is acquired 100 CDO O Connect to the CDI pin on the next chip when cascade connection is used. 89 DISPOFF I Input that controls the O1 to O80 output pins. During periods when this pin Is low, the O1 to O80 output pins output the V1 level. See the truth table. 1 to 80 O1 to O80 O LCD drive outputs The output level are determined by the combination of the output the data, The M signal, and The DISPOFF pin as shown in the table. M Q DISPOFF Output L L H V3 L H H V1 H L H V4 H H H VEE * * L V1 Note : don’t care (fixed at high or low) 92 NC 93 NC 94 NC - Must be left open. |
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