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ARM7TDMI Datasheet(PDF) 59 Page - ATMEL Corporation |
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ARM7TDMI Datasheet(HTML) 59 Page - ATMEL Corporation |
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59 / 284 page  Programmer’s Model ARM DDI 0029G Copyright © 1994-2001. All rights reserved. 2-13 2.7 The program status registers The ARM7TDMI processor contains a CPSR and five SPSRs for exception handlers to use. The program status registers: • hold information about the most recently performed ALU operation • control the enabling and disabling of interrupts • set the processor operating mode. The arrangement of bits is shown in Figure 2-6. Figure 2-6 Program status register format Note To maintain compatibility with future ARM processors, you must not alter any of the reserved bits. One method of preserving these bits is to use a read-write-modify strategy when changing the CPSR. The remainder of this section describes: • Condition code flags on page 2-13 • Control bits on page 2-14 • Reserved bits on page 2-15. 2.7.1 Condition code flags The N, Z, C, and V bits are the condition code flags, you can set them by arithmetic and logical operations. They can also be set by MSR and LDM instructions. The ARM7TDMI processor tests these flags to determine whether to execute an instruction. 31 30 29 28 27 26 25 24 23 8 7 6 4 3 2 1 0 Reserved Condition code flags Control bits Mode bits State bit FIQ disable IRQ disable Overflow Carry or borrow or extend Zero Negative or less than 5 N Z C V • • • • • • I F M4 M3 M2 M1 M0 T |
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