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HSDL-7001-2500 Datasheet(PDF) 2 Page - Agilent(Hewlett-Packard)

Part No. HSDL-7001-2500
Description  IR 3/16 Encode/Decode IC
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Maker  HP [Agilent(Hewlett-Packard)]
Homepage  http://www.home.agilent.com
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HSDL-7001-2500 Datasheet(HTML) 2 Page - Agilent(Hewlett-Packard)

   
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I/O Pinout List
Pin
Name
Type
Function
1
16XCLK
DIGIN
Positive edge triggered input clock that is set to 16 times the data
(SIXTNCK)
transmission baud rate. The encode and decode schemes require this
signal. The signal is usually tied to a UART’s BAUDOUT signal. The
16XCLK may be provided by application circuitry if BAUDOUT is not
available. This signal is required when the internal clock is not used.
2
/TXD
DIGIN
Negative edge triggered input signal that is normally tied to the SOUT
signal of the UART (serial data to be transmitted). Data is modulated
and output as IR_TXD.
3
RCV
DIGOUT
Output signal normally tied to SIN signal of a UART (received serial
data). RCV is the demodulated output of IR_RVC.
4
A0
DIGIN
Clock Multiplex Signal
5
A1
DIGIN
Clock Multiplex Signal
6
A2
DIGIN
Clock Multiplex Signal
7
CLK_SEL
DIGIN
Used to activate either the Internal or External Clock. A high on this
line activates the External clock (16XCLK) and a low activates the
Internal clock. When the External clock is activated, the internal
oscillator is put in POWERDOWN MODE.
8
GND
Chip Ground
9
/NRST
DIGIN
Active low signal used to reset the IrDA-SIR DECODE state machine.
This signal can be tied to POR (Power On Reset) or VCC. This signal can
also be used to disable any data reception.
10
/IR_RCV
DIGIN
Input from SIR optoelectronics. Input signal is a 3/16th or 1.6
µs pulse
which is demodulated to generate RCV output signal.
11
IR_TXD
DIGOUT
This is the modulated TXD signal.
12
PULSEMOD
DIGIN
A high level on this input puts the chip into the monoshot transmit
(with
mode. In this mode, when there is a negative transition on the TXD
pulldown)
input, a rising edge on the internal transmit modulation state machine
will activate a high pulse on IR_TXD for 6 crystal clock cycles. With a
3.6864 MHz crystal, this corresponds to 1.63
µs. This mode cannot be
used in conjunction with the 16XCLK clock. It is meant to be used with
the external crystal clock. By default, this input pin is pulled to GND.
13
POWERDN
DIGIN
A high on this input puts only the internal oscillator cell (OSCII) in
(with
POWERDOWN MODE. The cell is normally not powered down.
pulldown)
14
OSCOUT
ANAOUT
Oscillator Output
15
OSCIN
ANAIN
Oscillator Input
16
VCC
Power
Note: There are two methods of putting the internal oscillator cell in POWERDOWN MODE. Whenever the CLKSEL Pin is asserted
high (External clock selected) the oscillator cell is automatically put in powerdown mode, or whenever the POWERDN Pin is asserted
high.


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