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HSDL-7000 Datasheet(PDF) 3 Page - Agilent(Hewlett-Packard)

Part No. HSDL-7000
Description  IR 3/16 Encode/Decode IC
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Maker  HP [Agilent(Hewlett-Packard)]
Homepage  http://www.home.agilent.com
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HSDL-7000 Datasheet(HTML) 3 Page - Agilent(Hewlett-Packard)

   
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Encoding Scheme
Decoding Scheme
16 X CLOCK
16 CLOCK CYCLES
TXD
IRTXD
7 cs
3 cs
The encoder sends a pulse for
every space or “0” that is sent on
the TXD line. On a high to low
transition of the TXD line, the
generation of the pulse is delayed
for 7 clock cycles of the 16XCLK
before the pulse is set high for 3
clock cycles (or 3/16th of a bit
time) and then subsequently
pulled low.
A high to low transition of the
IR_RXD line from the HSDL-1000
signifies a 3/16th pulse. This
pulse is stretched to accommo-
date 1 bit time (16 clock cycles).
Every pulse that is received is
translated into a “0” or space on
the RXD line equal to 1 bit time.
Note: The stretched pulse must
be at least 3/4 of a bit time in
duration to be correctly
interpreted by a UART.
16 X CLOCK
16 CLOCK CYCLES
IR_RXD
RXD
3 cs


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